KR100264519B1 - Method for fabricating bipolar transistor - Google Patents

Abstract

A bipolar transistor manufacturing method according to the present invention includes the steps of forming an n-type second semiconductor layer on an n + -type first semiconductor layer; Forming a p-type third semiconductor layer in the second semiconductor layer; Forming an n + type fourth semiconductor layer in the third semiconductor layer; Selectively doping a high concentration of n-type impurities only to the back surface of the first semiconductor layer; Simultaneously forming an emitter electrode connected to the fourth semiconductor layer and a base electrode connected to the third semiconductor layer on the second semiconductor layer; And forming a collector electrode on the back surface of the first semiconductor layer, 1) increasing the n + concentration of the back surface of the first semiconductor layer to ˜10 ¹⁹ cm ⁻³ , thereby providing an ohmic contact between the first semiconductor layer and the collector electrode. The characteristics can be improved, and 2) forward voltage and power consumption can also be reduced.

Description

Bipolar Transistor Manufacturing Method

The present invention relates to a bipolar transistor manufacturing method, and more particularly to a method for manufacturing a bipolar transistor to improve the ohmic contact characteristics to reduce the forward voltage of the transistor.

In the conventional npn bipolar transistor, as shown in the cross-sectional view of FIG. 1, a collector electrode 12 is formed on a lower surface of an n + type first semiconductor layer 10, and the first semiconductor layer 10 is formed on an upper surface thereof. ) And an n-type second semiconductor layer 14 serving as a collector are formed, and a p-type third semiconductor layer 16 serving as a base is formed in the second semiconductor layer 14. An n-type fourth semiconductor layer 18 serving as an emitter is formed in the third semiconductor layer 16, and an emitter electrode connected to the fourth semiconductor layer 18 on the second semiconductor layer 14. It can be seen that the base electrode 22 connected to the 20 and the third semiconductor layer 16 has a structure formed to be spaced apart from each other with an insulating layer (not shown) therebetween.

Therefore, the npn bipolar transistor of the above structure is largely manufactured through the following sixth step as shown in the process block diagram shown in FIG.

As a first step 100, an n + type first semiconductor layer 10 is prepared.

As a second step 102, an n-type second semiconductor layer 14 is formed on the first semiconductor layer 10.

As a third step 104, a p-type third semiconductor layer 16 is formed in the second semiconductor layer 14 through a p-type impurity implantation and diffusion process.

As a fourth step 106, an n + type fourth semiconductor layer 18 is formed in the p type third semiconductor layer 16 through an n + type impurity implantation and diffusion process.

In a fifth step 108, an emitter electrode connected to the fourth semiconductor layer 18 and a base electrode 24 connected to the third semiconductor layer 16 are simultaneously formed through a conductive film deposition and etching process.

As the sixth step 110, the collector electrode 12 made of the conductive film material is formed on the lower surface of the first semiconductor layer 10, thereby completing the process.

However, when the bipolar transistor is manufactured through the above process, the following problem occurs. When the epitaxial wafer is used as the first semiconductor layer 10, the n + concentration on the back side of the wafer usually has a low concentration value of about 10 ¹⁸ cm ⁻³ . Therefore, when the collector electrode 12 is formed on the back surface of the first semiconductor layer 10 in this state, the conductive film constituting the electrode and the first semiconductor layer 10 cannot make good ohmic contact, and thus the collector electrode The problem that the ohmic contact between (12) and the first semiconductor layer 10 becomes large will occur. When such a problem occurs, the forward voltage is increased while driving the bipolar transistor, and power consumption is also increased. Therefore, there is an urgent need for improvement.

Accordingly, an object of the present invention is to further improve the ohmic contact resistance between the first semiconductor layer and the collector electrode by doping a high concentration of n-type impurities to the back surface of the first semiconductor layer after forming the fourth semiconductor layer serving as an emitter. It is an object of the present invention to provide a bipolar transistor manufacturing method capable of reducing the forward voltage when driving the device.

1 is a cross-sectional view showing the structure of a typical npn bipolar transistor;

FIG. 2 is a process block diagram showing a bipolar transistor manufacturing method shown in FIG.

FIG. 3 is a process block diagram showing a bipolar transistor manufacturing method shown in FIG. 1 according to the present invention.

In order to achieve the above object, the present invention provides a process for forming an n-type second semiconductor layer on an n + -type first semiconductor layer; Forming a p-type third semiconductor layer in the second semiconductor layer; Forming an n + type fourth semiconductor layer in the third semiconductor layer; Selectively doping a high concentration of n-type impurities only to the back surface of the first semiconductor layer; Simultaneously forming an emitter electrode connected to the fourth semiconductor layer and a base electrode connected to the third semiconductor layer on the second semiconductor layer; And a process of forming a collector electrode on a back surface of the first semiconductor layer.

In the case of manufacturing the bipolar transistor through the above process, the impurity doping concentration of the first semiconductor layer back surface is increased to ˜10 ¹⁹ cm ⁻³ due to the high concentration of n-type impurities doped on the back surface of the first semiconductor layer. In forming the electrode, contact resistance between the first semiconductor layer and the conductive film forming the collector electrode can be reduced.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

According to the present invention, a bipolar transistor is manufactured by forming a collector electrode 12 in a state in which a high concentration of n-type impurities are separately doped on a white surface of the first semiconductor layer 10, thereby manufacturing the first semiconductor layer 10. It is a technique focused on making it possible to improve the ohmic contact characteristic between the collector electrode 12 and.

In the case of the present invention, since the basic structure of the npn bipolar transistor is the same as the conventional structure shown in FIG. 1, the manufacturing method of the npn bipolar transistor is different from the conventional method with reference to the process block diagram shown in FIG. Look at each step.

As a first step 200, an n + type first semiconductor layer 10 to be used as a collector is prepared.

As a second step 202, an n-type second semiconductor layer 14 to be used as a collector is formed on the first semiconductor layer 10.

In a third step 204, an insulating layer (not shown) of an oxide film is formed on the second semiconductor layer 14, and the semiconductor layer 14 is exposed so that the surface of the second semiconductor layer 14 of the base forming portion is exposed. The insulating layer on the upper surface is partially etched. Subsequently, an oxide layer buffer layer (not shown) is formed on the surface exposed portion of the second semiconductor layer 14, and ion implanted BF ₃ , which is a p-type impurity, is diffused through a heat treatment process. The p-type third semiconductor layer 16 to be used as a base is formed in the semiconductor layer 14.

As a fourth step 206, the buffer layer is removed, and an insulating film (not shown) made of an oxide film is formed again in the portion where the buffer layer is removed so that the entire surface of the second semiconductor layer 14 is protected by the insulating layer. In order to expose the surface of the second semiconductor layer 14 of the emitter forming unit, the insulating layer on the upper surface of the second semiconductor layer 14 is partially etched, and the buffer layer of the oxide film material is exposed to the surface exposed portion of the second semiconductor layer 14. (Not shown). Subsequently, a high concentration of n-type impurity PH ₃ is ion-implanted onto the buffer layer and diffused through a heat treatment process to form an n + -type fourth semiconductor layer 18 to be used as an emitter in the third semiconductor layer 16. do.

In a fifth step 208, the buffer layer is removed, and an insulating film (not shown) made of an oxide film is formed on the portion where the buffer layer is removed so that the entire surface of the second semiconductor layer 14 is protected by the insulating layer. PH ₃ , which is a high concentration n-type impurity (n + -type impurity), is doped on the white surface (a portion where the surface is exposed) of the first semiconductor layer 10. As a result, the higher is the concentration of from 1 to the n + semiconductor layer 10 baekmyeon ^{~ 10 18 cm -3 ~ 10 19} cm -3.

As such, the addition of the n + type impurity doping process after the formation of the fourth semiconductor layer 18 increases the concentration of n + on the back surface of the first semiconductor layer 10 so that the first semiconductor layer (at the time of forming the collector electrode 12) This is to improve the ohmic contact characteristic between 10) and the collector electrode 12.

In a sixth step 210, the insulating layer on the upper surface of the second semiconductor layer 14 is partially etched so that the surfaces of the third semiconductor layer 16 and the fourth semiconductor layer 18 are partially exposed, and the entire surface of the resultant is etched. A conductive film having a predetermined thickness is formed on the substrate. Subsequently, a photolithography process is used to etch the conductive film in other portions except for the electrode forming portion, and the base electrode 22 connected to the third semiconductor layer 16 and the emitter electrode connected to the fourth semiconductor layer 18. (20) is formed simultaneously.

In the seventh step 212, the collector electrode 12 made of the conductive film is formed on the back surface of the first semiconductor layer 10, thereby completing the process.

In this way, the concentration of n + on the back surface of the first semiconductor layer 10 can be increased to 10 ¹⁹ cm ^-3 , so that the conductive film constituting the collector electrode 12 and the first semiconductor layer 10 are good. Ohmic contact can be achieved.

As described above, according to the present invention, after forming the fourth semiconductor layer used as the emitter when forming the npn bipolar transistor, by doping a high concentration of n-type impurities on the back surface of the first semiconductor layer, 1) first, because the n + concentration of the semiconductor layer baekmyeon can be increased up to ~ 10 ¹⁹ cm ^-3 of claim 1 being able to improve the ohmic contact characteristics between a semiconductor layer and a collector electrode, and 2) the device consuming the forward voltage and power during operation also reduces It becomes possible.

Claims (1)

forming an n-type second semiconductor layer on the n + -type first semiconductor layer; Forming a p-type third semiconductor layer in the second semiconductor layer; Forming an n + type fourth semiconductor layer in the third semiconductor layer; Selectively doping a high concentration of n-type impurities only to the back surface of the first semiconductor layer; Simultaneously forming an emitter electrode connected to the fourth semiconductor layer and a base electrode connected to the third semiconductor layer on the second semiconductor layer; And And forming a collector electrode on the back surface of the first semiconductor layer.