KR100192537B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100192537B1 KR100192537B1 KR1019960029209A KR19960029209A KR100192537B1 KR 100192537 B1 KR100192537 B1 KR 100192537B1 KR 1019960029209 A KR1019960029209 A KR 1019960029209A KR 19960029209 A KR19960029209 A KR 19960029209A KR 100192537 B1 KR100192537 B1 KR 100192537B1
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- insulating film
- semiconductor substrate
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000007769 metal material Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로서, 특히, 샐리사이드(salicide)를 사용한 소자의 쇼트 채널9short channel) 특성을 현저히 개선한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with remarkably improved short channel (9 channel) characteristics of a device using salicide.
이와 같은 본 발명의 실시예에 따른 반도체 소자 제조방법은, 반도체 기판 상에 게이트 절연막과 게이트 도전막을 형성한 후, 식각공정을 실시하여 게이트 전극을 형성하는 단계, 상기 반도체 기판 전면에 제1 절연막, 제2 절연막을 증착한 후, 이방성 식각 공정을실시하여 게이트 전극 측벽에 제1 및, 제2 측벽 스페이서를 형성하는 단계, 상기 노출된 반도체 기판 내에 이온 주입공정을 실시하여 소오스와 드레인을 형성한 후, 고온 열처리 공정을 실시하는 단계, 상기 반도체 기판 전면에 금속물질을 증착하여 샐리사이드(salicide) 공정을 실시하는 단계, 상기 제2 측벽 스페이서를 제거하는 단계 및, 상기 노출된 반도체 기판 전면에 이온 주입 공정을 실시하여 LDD 영역을 형성하는 단계를 포함하여 구성된다.In the semiconductor device manufacturing method according to the embodiment of the present invention, after forming a gate insulating film and a gate conductive film on a semiconductor substrate, performing a etching process to form a gate electrode, the first insulating film, the entire surface of the semiconductor substrate, After depositing the second insulating film, performing an anisotropic etching process to form the first and second sidewall spacers on the sidewalls of the gate electrode, and performing an ion implantation process in the exposed semiconductor substrate to form a source and a drain. Performing a high temperature heat treatment process, depositing a metal material on the entire surface of the semiconductor substrate, performing a salicide process, removing the second sidewall spacer, and implanting ions into the exposed surface of the semiconductor substrate. And performing the process to form the LDD region.
Description
본 발명은 반도체 소자 제조방법에 관한 것으로서, 특히, 샐리사이드 (salicide)를 사용한 소자의 쇼트 채널(short channel) 특성을 현저히 개선한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with remarkably improved short channel characteristics of a device using salicide.
이하 첨부한 도면을 참조로 하여 종래기술에 의한 반도체 소자의 제조방법을 알아 보기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
제1a도 내지 1d도는 종래기술에 의한 반도체 제조방법을 나타낸 공정 단면도이다.1A to 1D are cross-sectional views illustrating a semiconductor manufacturing method according to the prior art.
우선, 제1a도와 같이 실리콘 기판(10) 상에 게이트 절연막(11)과 폴리실리콘막(12)을 증착한다. 이어서 상기 폴리실리콘막에 식각공정을 실시하여 게이트 전극(11, 12)을 형성한다.First, as shown in FIG. 1A, a gate insulating film 11 and a polysilicon film 12 are deposited on the silicon substrate 10. Subsequently, the polysilicon film is etched to form gate electrodes 11 and 12.
그다음 제1b도에 나타난 바와 같이 저농도의 이온 주입 공정을 실시하여 실리콘 기판(10) 표면 내에 LDD(Lightly Doped Drain) 영역(13)을 형성한다.Next, as shown in FIG. 1B, a low concentration ion implantation process is performed to form a lightly doped drain (LDD) region 13 in the silicon substrate 10 surface.
제1c도에 도시된 바와 같이 상기 실리콘 기판 전면에 절연막(14)을 증착한 후, 상기 절연막(14a)에 이방성 식각공정을 실시하여 게이트 전극 양측면에 측벽 스페이서 (14a)를 형성한다. 이어 상기 게이트 전극 및, 측벽 스페이서를 마스크로 고농도의 이온주입을 실시하여 소오스와 드레인 영역(15)을 형성한 후, 고온 열처리 공정을 실시한다.As illustrated in FIG. 1C, after the insulating film 14 is deposited on the entire surface of the silicon substrate, an anisotropic etching process is performed on the insulating film 14a to form sidewall spacers 14a on both sides of the gate electrode. Subsequently, a high concentration of ions are implanted using the gate electrode and sidewall spacers as a mask to form a source and a drain region 15, and then a high temperature heat treatment process is performed.
제1d도에 나타난 바와 같이 금속물질 예컨대, 티타늄(Ti)이나 코발트(Co)를 증착하여 700℃ 이하의 저온 열처리 공정을 실시하여 샐리사이드 공정을 수행한다. 이때, 상기 금속물질은 게이트 전극 및, 소오스와 드레인 영역에서만 반응하여 샐리사이드(16)를 이루게 된다. 이어서, 미반응된 금속물질을 습식식각 공정으로 제거하고 다시 2차적으로 850℃ 이하의 온도에서 열처리 공정을 실시한다.As shown in FIG. 1d, a metal material such as titanium (Ti) or cobalt (Co) is deposited to perform a low temperature heat treatment process at 700 ° C. or lower to perform a salicide process. In this case, the metal material reacts only with the gate electrode and the source and drain regions to form the salicide 16. Subsequently, the unreacted metal material is removed by a wet etching process, and secondly, a heat treatment process is performed at a temperature of 850 ° C. or lower.
종래기술에 의한 반도체 소자 제조방법에서는 샐리사이드(salicide) 공정이 저항을 줄여줌으로써 상대적으로 소자의 특성을 개선하는 장점이 있으나, 샐리사이드 공정이 실리콘을 소모하므로 상대적으로 고농도의 소오스/드레인 접합(junction)이 필요한 단점이 있다. 이로인해 기존 공정의 경우 고온 열처리를 소오스/드레인 이온 주입후 실시하여 상대적으로 LDD 부분의 접합도 길어지는 문제가 발생한다. 이로인해 소자의 쇼트 채널 특성이 나빠지고, 집적도 개선의 한계로 작용하는 문제가 있다.In the semiconductor device manufacturing method according to the prior art, the salicide process has the advantage of relatively improving the characteristics of the device by reducing the resistance, but since the salicide process consumes silicon, a relatively high concentration source / drain junction ) Is a disadvantage. As a result, in the conventional process, high temperature heat treatment is performed after source / drain ion implantation, thereby causing a relatively long bonding of LDD parts. As a result, the short channel characteristic of the device is deteriorated, which causes a problem of limiting the degree of integration.
본 발명은 상기한 종래의 문제점을 해결하기 위하여 제안된 것으로서, 쇼트 채널 특성을 개선하면서 샐리사이드 공정의 장점인 저항감소는 그대로 유지한 반도체 소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a method of manufacturing a semiconductor device in which the resistance reduction, which is an advantage of the salicide process, is maintained while improving the short channel characteristics.
제1a도 내지 1d도는 종래기술에 의한 반도체 소자 제조방법을 도시한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
제2a도 내지 2d도는 본 발명의 실시예에 따른 반도체 소자 제조방법을 도시한 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 실리콘 기판 21 : 게이트 절연막20 silicon substrate 21 gate insulating film
22 : 폴리실리콘막 23a : 제1 측벽 스페이서22 polysilicon film 23a first sidewall spacer
24a : 제2 측벽 스페이서 25 : 소오스/드레인 영역24a: second sidewall spacer 25: source / drain regions
26 : 샐리사이드 27 : LDD 영역26: salicide 27: LDD region
본 발명에 따른 반도체 소자 제조방법은, 반도체 기판 상에 게이트 절연막과 게이트 도전막을 형성한 후, 식각공정을 실시하여 게이트 전극을 형성하는 단계; 상기 반도체 기판 전면에 제1 절연막, 제2 절연막을증착한 후, 이방성 식각 공정을 실시하여 게이트 전극 측벽에 제1 및, 제2 측벽 스페이서를 형성하는단계; 상기 노출된 반도체 기판 내에 이온 주입공정을 실시하여 소오스와 드레인을 형성한후, 고온 열처리 공정을 실시하는 단계; 상기 반도체 기판 전면에 금속물질을 증착하여 샐리사이드(salicide) 공정을 실시하는 단계; 상기 제2 측벽 스페이서를 제거하는 단계; 및, 상기 노출된 반도체 기판 전면에 이온 주입 공정을 실시하여 LDD 영역을 형성하는 단계를 포함하여 구성된다.In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a gate insulating film and a gate conductive film on a semiconductor substrate, and then performing a etching process to form a gate electrode; Depositing a first insulating film and a second insulating film on the entire surface of the semiconductor substrate, and then performing an anisotropic etching process to form first and second sidewall spacers on sidewalls of the gate electrode; Performing an ion implantation process in the exposed semiconductor substrate to form a source and a drain, and then performing a high temperature heat treatment process; Depositing a metal material on the entire surface of the semiconductor substrate to perform a salicide process; Removing the second sidewall spacer; And forming an LDD region by performing an ion implantation process on the entire exposed semiconductor substrate.
이하 첨부한 도면을 참조하여 본 발명을 더욱 상세하게 설명하면 다음과 같다. 제2a도 내지 제2d도는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 단면도이다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. 2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
우선, 제2a도와 같이 실리콘 기판(20) 상에 게이트 절연막(21)과 폴리실리콘막(22)을 증착한다. 이어서 상기 폴리실리콘막에 식각공정을 실시하여 게이트 전극(21, 22)을 형성한다.First, as shown in FIG. 2A, a gate insulating film 21 and a polysilicon film 22 are deposited on the silicon substrate 20. Subsequently, the polysilicon film is etched to form gate electrodes 21 and 22.
그 다음, 제2b도에 나타난 바와 같이 상기 실리콘 기판(20) 상에 제1 절연막 예컨대, 실리콘 산화막(23)과 제2 절연막으로서 예컨대, 실리콘 질화막(24)을 증착한다. 이어서, 상기 실리콘 질화막(24)에 이방성 식각 공정을 실시하여 게이트 전극 양측면에 제1 측벽 스페이서(23a)와 제2 측벽 스페이서(24a)를 형성한다. 이어서, 상기 노출된 실리콘 기판(20)상에 고농도의 이온 주입 공정을 실시하여 소오스와 드레인 영역(25)을 형성한다. 또한, 이온주입 공정이 완료된 후, 어닐(anneal) 공정을 실시한다. 이때, 상기 어닐 공정은 대략 1000℃의 온도에서 RTA(Rapid Thermal Anneal) 공정 또는, 900℃의 온도에서 퍼어너스 어닐(Furnace Anneal) 공정으로 실시한다.Then, as shown in FIG. 2B, a silicon nitride film 24 is deposited on the silicon substrate 20 as a first insulating film, for example, a silicon oxide film 23 and a second insulating film. Subsequently, an anisotropic etching process is performed on the silicon nitride layer 24 to form first sidewall spacers 23a and second sidewall spacers 24a on both sides of the gate electrode. Subsequently, a high concentration ion implantation process is performed on the exposed silicon substrate 20 to form the source and drain regions 25. In addition, after the ion implantation process is completed, an annealing process is performed. In this case, the annealing process may be performed by a rapid thermal annealing (RTA) process at a temperature of approximately 1000 ° C. or a furnace annealing process at a temperature of 900 ° C.
한편, 상기 실리콘 산화막의 증착 두께는 100~300Å, 상기 실리콘 질화막의 증착 두께는 700~1000Å으로 하는 것이 바람직하다.On the other hand, it is preferable that the deposition thickness of the silicon oxide film is 100 to 300 kPa, and the deposition thickness of the silicon nitride film is 700 to 1000 kPa.
또 제2c도에 도시된 바와 같이 금속물질 예컨대, 티타늄(Ti) 이나 코발트(Co)를 증착하여 700℃ 이하의 저온 열처리 공정을 실시하여 샐리사이드 공정을 수행한다. 이때, 상기 금속물질은 게이트 전극 및, 소오스와 드레인 영역에서만 반응하여 샐리사이드(26)를 이루게 된다. 이어서, 미반응된 금속물질을 습식식각 공정으로 제거하고 다시 2차적으로 850℃ 이하의 온도에서 열처리 공정을 실시한다.In addition, as shown in FIG. 2c, a metal material such as titanium (Ti) or cobalt (Co) is deposited to perform a low temperature heat treatment process at 700 ° C. or lower to perform a salicide process. In this case, the metal material reacts only with the gate electrode and the source and drain regions to form the salicide 26. Subsequently, the unreacted metal material is removed by a wet etching process, and secondly, a heat treatment process is performed at a temperature of 850 ° C. or lower.
제2d도와 같이 상기 제2 측벽 스페이서(24a)를 제거한 후, 저농도의 이온주입을 실시하여 LDD 영역(27)을 형성한다. 이때, 경사(tilt) 이온 주입과 비경사(no-tilt) 이온 주입을 실시하여 LDD 영역(27)을 형성한다.After removing the second sidewall spacer 24a as shown in FIG. 2D, low concentration ion implantation is performed to form the LDD region 27. At this time, the tilt ion implantation and the non-tilt ion implantation are performed to form the LDD region 27.
본 발명에 따른 반도체 소자 제조방법에 의하면, LDD 영역을 형성하기 위한 이온 주입을 샐리사이드 공정이 완료된 후 실시함으로써, 기존 샐리사이드(salicide) 공정의 장점인 저항감소는 그대로 유지하면서도 LDD 접합 영역의 깊이를 감소시켜 쇼트 채널(short channel) 특성의 악화를 해결해 주는 효과가 있다.According to the method of manufacturing a semiconductor device according to the present invention, the ion implantation for forming the LDD region is performed after the salicide process is completed, so that the depth of the LDD junction region is maintained while maintaining the resistance, which is an advantage of the conventional salicide process. The effect of reducing the deterioration of the short channel characteristic is reduced.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960029209A KR100192537B1 (en) | 1996-07-19 | 1996-07-19 | Method of manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960029209A KR100192537B1 (en) | 1996-07-19 | 1996-07-19 | Method of manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR980012124A KR980012124A (en) | 1998-04-30 |
| KR100192537B1 true KR100192537B1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960029209A Expired - Fee Related KR100192537B1 (en) | 1996-07-19 | 1996-07-19 | Method of manufacturing semiconductor device |
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| Country | Link |
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| KR (1) | KR100192537B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100866732B1 (en) * | 2002-07-09 | 2008-11-03 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
| KR100906500B1 (en) * | 2002-11-26 | 2009-07-08 | 매그나칩 반도체 유한회사 | Method of manufacturing gate of semiconductor device |
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1996
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| KR980012124A (en) | 1998-04-30 |
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