KR100486649B1 - Method for forming salicide of a semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a silicide of a semiconductor device, the method comprising: forming an amorphous poly film in a region where a silicide layer of a semiconductor structure is to be formed, depositing a silicide forming source on the entire surface of the structure, and heat treating the structure to form a silicide layer And removing the silicide forming source by etching some regions other than the region where the silicide layer is formed, and the silicide layer is thickly formed by an amorphous poly film, thereby lowering the resistance of the gate wiring, thereby reducing the electrical characteristics of the semiconductor device. This has the advantage of being improved.

Description

Method for forming silicide of semiconductor device {METHOD FOR FORMING SALICIDE OF A SEMICONDUCTOR DEVICE}

The present invention relates to a method of forming a silicide of a semiconductor device, and more particularly, to a method of forming a silicide of a semiconductor device in which an amorphous poly film which facilitates movement of silicon ions is formed in a region where a silicide layer is to be formed, so that the silicide layer is formed thick. It is about.

The silicide process is performed in order to reduce the resistance of the source / drain diffusion region and the gate wiring after forming the source / drain and lightly doped drain (LDD) regions during transistor formation. After sputtering a material such as Ti), the metal on the oxide layer is a series of processes for removing metals in regions other than the source / drain and the gate through wet etching since no reaction occurs.

Particularly, in the logic device that needs to realize high speed, there is a big problem in performance due to the increase of the gate resistance and the resistance of the contact. In terms of structure, first, when the contact hole size is reduced, the contact resistance value is not guaranteed. It causes delay in phase and does not realize high speed as a whole. Second, since the sheet resistance is large in the conventional diffusion structure, the contact resistance with the wiring is also large. This is also a fatal obstacle for logic devices that require high speeds. Therefore, a silicide process that can reduce the contact resistance by improving the diffusion sheet resistance is adopted.

1A to 1D are cross-sectional views of a semiconductor device employing a silicide process according to the related art, and are a general technique of improving silicidation in a poly gate electrode and a source / drain region of a MOSFET device to improve operating characteristics of the device.

First, the device isolation layer 2 is formed in the device isolation region of the semiconductor substrate 1 by field oxidation or shallow trench isolation (STI). In the process of forming the device isolation layer 2, an active region in which an actual device is to be formed is defined.

An oxide film and a polysilicon layer are formed in the active region and selectively patterned to form a gate oxide film 3 and a gate electrode 4, and a gate sidewall 5 is formed on the side of the gate electrode 4.

Impurity ions are implanted under the active region substrates on both sides of the gate electrode 4 to form the source / drain regions 6 (see FIG. 1A).

Next, ion implantation (↓) is performed in the active region to amorphous the silicon interface (see FIG. 1B).

Then, the silicide forming source 7 is sputtered and deposited on the entire structure. Here, the silicide-forming source 7 is made of a group 8 metal element (Ni, Co, Pt or the like) or titanium (Ti) or the like (see FIG. 1C).

Thereafter, the annealing process is performed to form the silicide layer 8, and the region except for the top of the source / drain and the gate is wet-etched to remove the silicide forming source 7 which is not reacted with silicon ions (see FIG. 1D).

However, the semiconductor device manufactured according to the prior art as described above did not form the silicide layer to a satisfactory level. Accordingly, the resistance of the gate wiring was high, resulting in a decrease in electrical characteristics of the semiconductor device.

The present invention has been proposed to solve such a conventional problem, by forming an amorphous poly film that facilitates the movement of silicon ions in the region where the silicide layer is to be formed, so that the silicide layer is formed thick, thereby lowering the resistance of the gate wiring to the semiconductor device. The purpose is to improve the electrical properties of the.

The silicide formation method of a semiconductor device according to the present invention for achieving the above object is a silicide formation method of a semiconductor device in which a silicide layer is formed in an active region of a semiconductor structure in which the devices are formed, thereby improving operating characteristics. Forming a device isolation layer defining an active region, forming and selectively patterning an oxide film and a polysilicon layer in the active region to form a gate oxide film and a gate electrode, and forming a gate sidewall on the side of the gate electrode Forming a source / drain region by implanting impurity ions into the lower portion of the active region substrate on both sides of the gate electrode, and forming the amorphous poly layer on the entire surface of the structure in which the source / drain region is formed; The source / drain region and the gay Etching and partially removing the amorphous poly film in a region other than the upper electrode region, depositing a silicide forming source on the entire surface of the structure, heat treating the structure to form a silicide layer, and the silicide layer is Etching the partial region except the formed region to remove the silicide forming source.

There may be a plurality of embodiments of the present invention. Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. This embodiment allows for a better understanding of the objects, features and advantages of the present invention.

2A to 2E are cross-sectional views of a semiconductor device employing a silicide process according to the present invention.

First, the device isolation layer 102 is formed in the device isolation region of the semiconductor substrate 101 by field oxidation or shallow trench isolation (STI). The formation process of the device isolation layer 102 defines an active region in which an actual device is to be formed.

An oxide film and a polysilicon layer are formed in the active region and selectively patterned to form a gate oxide film 103 and a gate electrode 104, and a gate sidewall 105 is formed on the side of the gate electrode 104.

Impurity ions are implanted under the active region substrates on both sides of the gate electrode 104 to form the source / drain regions 106 (see FIG. 2A).

Next, an amorphous poly film 201 is formed on the entire surface of the structure under a temperature condition of 500 to 550 ° C. in the furnace. At this time, the amorphous poly film 201 is preferably formed to a thickness of 400 ~ 700 400. The amorphous poly film 201 facilitates the movement of silicon ions during subsequent silicide formation to facilitate silicide formation (see FIG. 2B).

Subsequently, the amorphous poly film 201 is partially removed by wet etching a region in which a silicide layer is to be formed, that is, regions other than the source / drain and gate upper regions in a later process (see FIG. 2C).

Thereafter, the silicide forming source 107 is deposited on the front surface of the structure by sputtering. Here, the silicide-forming source 107 is made of a group 8 metal element (Ni, Co, Pt, etc.) or a material such as titanium (Ti). (See Fig. 2D).

Next, the silicide layer 208 is formed by annealing to form the silicide layer 208. At this time, the amorphous poly film 201 facilitates the movement of silicon ions, and the silicide layer 208 is sufficiently thick. Thereafter, the regions except for the source drain and the upper gate are wet-etched to remove the silicide forming source 107 that has not reacted with the silicon ions (see FIG. 2E).

In the above described preferred embodiments of the present invention and shown in the drawings, it is apparent that the present invention can be implemented in various embodiments by those skilled in the art. Such modified embodiments should be included in the technical spirit shown through the claims of the present invention.

As described above, the silicide layer is thickly formed by the amorphous poly film, thereby lowering the resistance of the gate wiring, thereby improving the electrical characteristics of the semiconductor device.

1A to 1E are cross-sectional views illustrating a silicide forming method of a semiconductor device according to the prior art;

2A to 2E are cross-sectional views illustrating a silicide forming method of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 102 device isolation layer

103 gate oxide film 104 gate electrode

105: gate sidewall 106: source / drain region

107: silicide forming source 201: amorphous poly film

208: silicide layer

Claims (4)

A method of forming a silicide of a semiconductor device in which a silicide layer is formed in an active region of a semiconductor structure in which devices are formed, thereby improving operating characteristics. Forming a device isolation layer defining an active region in the semiconductor substrate, Forming a gate oxide film and a gate electrode by forming and selectively patterning an oxide film and a polysilicon layer in the active region; Forming a gate sidewall at a side of the gate electrode; Implanting impurity ions into the active region substrate on both sides of the gate electrode to form a source / drain region; Forming the amorphous poly film on an entire surface of the structure in which the source / drain regions are formed; Etching and partially removing the amorphous poly film in a region excluding the source / drain region and the gate electrode upper region; Depositing a silicide forming source on the entire surface of the structure; Heat treating the structure to form a silicide layer; Etching the partial region except the region in which the silicide layer is formed to remove the silicide forming source Silicide forming method of a semiconductor device comprising a. delete The method of claim 1, The amorphous poly film is a silicide forming method of a semiconductor device, characterized in that formed in the furnace at a temperature of 500 ~ 550 ℃. The method of claim 1, And the amorphous poly film is formed to a thickness of 400 to 700 GPa.