KR0146522B1 - Transistor manufacturing method of semiconductor device - Google Patents
Transistor manufacturing method of semiconductor deviceInfo
- Publication number
- KR0146522B1 KR0146522B1 KR1019950006092A KR19950006092A KR0146522B1 KR 0146522 B1 KR0146522 B1 KR 0146522B1 KR 1019950006092 A KR1019950006092 A KR 1019950006092A KR 19950006092 A KR19950006092 A KR 19950006092A KR 0146522 B1 KR0146522 B1 KR 0146522B1
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- oxide film
- region
- film
- gate electrode
- polysilicon layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims description 26
- 150000002500 ions Chemical class 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 239000005368 silicate glass Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/351—Substrate regions of field-effect devices
- H10D62/357—Substrate regions of field-effect devices of FETs
- H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
- H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, P형 MOS 트랜지스터를 제조함에 있어, 쇼트채널효과(Short Channel Effect)를 억제시키기 위하여 실리콘기판에 N+영역을 형성하고 BSG(Boron Silicate Glass)막을 이용하여 상기 N+영역 상부에 P--층이 형성되도록 하므로써 얕은 접합깊이(Shallow Junction Depth)를 갖는 접합영역을 형성하며 높은 전달콘덕턴스(Trans Conductance)를 이룰 수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In manufacturing a P-type MOS transistor, an N + region is formed on a silicon substrate and a BSG (Boron Silicate Glass) film is formed in order to suppress a short channel effect. Method of manufacturing a transistor of a semiconductor device to form a junction region having a shallow junction depth by forming a P - layer on the N + region by using a high transconductance It is about.
Description
제1a 및 제1b도는 종래 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a transistor manufacturing method of a conventional semiconductor device.
제2a 내지 제2e도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of elements for explaining the first embodiment of the present invention.
제3a 내지 제3c도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도.3A to 3C are cross-sectional views of elements for explaining the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 10 : 실리콘기판 2 및 22 : N웰1 and 10: silicon substrate 2 and 22: N well
3,23 및 33 : 게이트산화막 4,14 및 34 : 게이트전극3,23 and 33: gate oxide films 4,14 and 34: gate electrodes
5 : LDD영역 6,16 및 26 : 산화막스페이서5: LDD region 6, 16 and 26: oxide spacer
7,17 및 27 : 접합영역 11 및 21 : 산화막7,17 and 27: junction regions 11 and 21: oxide film
12 : N+영역 13 및 15 : 제1 및 제2 BSG막12: N + region 13 and 15: first and second BSG film
20 및 24 : P--층 18 및 28 : P-영역20 and 24: P - Layers 18 and 28: P - Regions
19 : BSG막19: BSG film
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 특히 P형 MOS 트랜지스터를 제조함에 있어, 쇼트채널효과(Short Channel Effect)를 억제시키기 위하여 실리콘기판에 N+영역을 형성하고 BSG(Boron Silicate Glass)막을 이용하여 상기 N+영역 상부에 P--층이 형성되도록 하므로써 얕은 접합깊이(Shallow Junction Depth)를 갖는 접합영역을 형성하며 높은 전달콘덕턴스(Trans Conductance)를 이룰 수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In particular, in manufacturing a P-type MOS transistor, an N + region is formed on a silicon substrate and a BSG (Boron Silicate Glass) is formed in order to suppress a short channel effect. Fabrication of transistors in semiconductor devices that form a junction region with shallow junction depth and achieve high transconductance by forming a P - layer on the N + region using a film It is about a method.
일반적으로 반도체 소자의 고집적화에 따라 N형 및 P형 트랜지스터를 구비하는 C-MOS소자의 제조에 있어, P형 MOS 트랜지스터는 N형 MOS 트랜지스터에 비하여 쇼트채널효과면에서 매우 취약한 단점을 가지고 있다. 그러면 종래 반도체 소자의 트랜지스터 제조방법을 제1a 및 제1b도를 통해 설명하면 다음과 같다.In general, in the manufacture of C-MOS devices having N-type and P-type transistors due to high integration of semiconductor devices, P-type MOS transistors have a weak point in terms of short channel effects compared to N-type MOS transistors. A method of manufacturing a transistor of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.
제1a도는 N웰(2)이 형성된 실리콘기판(1)상에 게이트산화막(3) 및 폴리실리콘층을 순차적으로 형성한 후 상기 폴리실리콘층에 불순물이온을 주입하고 게이트전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막(3)을 순차적으로 패터닝하여 게이트전극(4)을 형성한 다음 노출된 실리콘기판(1)에 LDD(Lightly Dopped Drain) 이온을 주입하여 LDD영역(5)을 형성한 상태의 단면도이다.FIG. 1A shows a gate oxide film 3 and a polysilicon layer sequentially formed on a silicon substrate 1 having an N well 2 formed therein, followed by implanting impurity ions into the polysilicon layer and using a mask for a gate electrode. The polysilicon layer and the gate oxide layer 3 are sequentially patterned through an etching process to form a gate electrode 4, and then LDD (Lightly Dopped Drain) ions are implanted into the exposed silicon substrate 1 (LDD region 5). It is sectional drawing of the state formed.
제1b도는 상기 게이트전극(4)의 양측벽에 산화막스페이서(6)를 형성한 후 고농도불순물이온을 주입하여 접합영역(7)을 형성한 상태의 단면도인데, 상기 게이트전극(4)에 N+형 불순물이온이 주입되는 경우 N형 MOS 트랜지스터와 동일한 N+형 폴리게이트(Poly gate)로 구성되어 제조단가면에서는 유리하나 쇼트채널효과에 취약한 단점을 가진다. 또한 상기 게이트전극(4)에 P+형 불순물이온이 주입되는 경우 상기 게이트전극(4)내의 붕소(B)가 게이트산화막(3)을 거쳐 실리콘기판(1)으로 침투되어 낮은 전달콘덕턴스를 갖는 단점이 있다.The 1b turning N + to inde after forming the oxide spacer 6 to the side walls by implanting high-concentration impurity ions are cross-sectional views of the formation of the joint region (7) state, the gate electrode 4 of the gate electrode 4 In the case of implanting impurity ions, it is composed of the same N + -type poly gate as the N-type MOS transistor. In addition, when P + type impurity ions are injected into the gate electrode 4, boron B in the gate electrode 4 penetrates into the silicon substrate 1 through the gate oxide film 3 and has a low transfer conductance. There are disadvantages.
따라서 본 발명은 실리콘기판에 N+영역을 형성하고 BSG막을 이용하여 상기 N+영역 상부에 P--층이 형성되도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for fabricating a transistor of a semiconductor device which can solve the above disadvantages by forming an N + region on a silicon substrate and forming a P − layer on the N + region using a BSG film. There is this.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜지스터 제조방법은 N웰이 형성된 실리콘기판상에 산화막을 성장시킨 후 N+형 불순물이온을 주입하고 열처리하여 상기 실리콘기판에 N+영역을 형성시키는 단계와, 상기 단계로 부터 상기 산화막을 제거한 후 전체면에 제1 BSG막을 증착하고 급속열처리공정을 실시하여 상기 N+영역의 상부에 P--층을 형성시키는 단계와, 상기 단계로 부터 상기 제1 BSG막을 제거한 후 게이트산화막 및 폴리실리콘층을 순차적으로 형성하고 상기 폴리실리콘층에 P+형 불순물이온을 주입한 후 게이트전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막을 순차적으로 패터닝하여 게이트전극을 형성한 다음 상기 게이트전극의 양측부에 산화막스페이서를 형성하는 단계와, 상기 단계로 부터 전체면에 제2 BSG막을 증착한 후 P+형 불순물이온을 주입하여 접합영역을 형성하고 급속열처리공정을 실시하는 단계와, 상기 단계로 부터 상기 제2 BSG막을 제거하는 단계로 이루어지는 것을 특징으로 하며, 다른 반도체 소자의 트랜지스터 제조방법은 실리콘기판상에 산화막을 성장시킨 후 N형 불순물이온을 주입하고 드라이브-인하여 N웰을 형성하는 단계와, 상기 단계로 부터 상기 산화막을 제거한 후 전체면에 BSG막을 증착하고 급속열처리공정을 실시하여 상기 N웰의 상부에 P--층을 형성시키는 단계와, 상기 단계로부터 상기 BSG막을 제거한 후 게이트산화막 및 폴리실리콘층을 순차적으로 형성하고 상기 폴리실리콘층에 P+형 불순물이온을 주입한 후 게이트전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막을 순차적으로 패터닝하여 게이트전극을 형성하는 단계와, 상기 단계로 부터 상기 게이트전극의 양측부에 산화막스페이서를 형성하고 P+형 불순물이온을 주입하여 접합영역을 형성한 후 열처리하는 단계로 이루어지는 것을 특징으로 한다.In the transistor manufacturing method of a semiconductor device according to the present invention for achieving the above object is formed by growing an oxide film on a silicon substrate on which N well is formed, implanting N + type impurity ions and heat treatment to form an N + region on the silicon substrate And depositing the first BSG film on the entire surface after removing the oxide film from the step, and performing a rapid heat treatment process to form a P − layer on the N + region. After the first BSG film is removed, the gate oxide film and the polysilicon layer are sequentially formed, the P + type impurity ions are injected into the polysilicon layer, and the polysilicon layer and the gate oxide film are subjected to a photo and etching process using a gate electrode mask. Patterning the sequential patterns to form a gate electrode, and then forming oxide film spacers on both sides of the gate electrode; And depositing a second BSG film on the entire surface from the above step, forming a junction region by injecting P + -type impurity ions, and performing a rapid heat treatment process, and removing the second BSG film from the step. The method of manufacturing a transistor of another semiconductor device includes growing an oxide film on a silicon substrate, implanting N-type impurity ions, and driving-in to form an N well; Depositing a BSG film on the surface and performing a rapid heat treatment process to form a P - layer on the N well, removing the BSG film from the step, and sequentially forming a gate oxide film and a polysilicon layer, and then forming the polysilicon. After injecting P + type impurity ions into the layer, the polysilicon layer and Patterning the gate oxide film sequentially to form a gate electrode, and forming an oxide spacer on both sides of the gate electrode, injecting P + -type impurity ions to form a junction region, and then performing heat treatment. It is characterized by.
이하, 본 발명의 실시예를 첨부한 도면을 참고하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
제2a 내지 제2e도는 본 발명의 제1 실시예를 설명하기 위한 소자의 단면도로서,2A through 2E are cross-sectional views of devices for describing the first embodiment of the present invention.
제2a도는 N웰(도시않됨)이 형성된 실리콘기판(10)상에 산화막(11)을 성장시킨후 N+형 불순물이온을 주입하고 열처리하여 상기 실리콘기판(10)에 N+영역(12)을형성한 상태의 단면도인데, 상기 N+영역(12)의 불순물 농도는 상기 N웰의 불순물농도보다 높게 주입된다.FIG. 2A shows that the N + region 12 is formed on the silicon substrate 10 by growing an oxide film 11 on the silicon substrate 10 having N wells (not shown), injecting N + -type impurity ions, and performing heat treatment. It is a cross-sectional view of the formed state, wherein the impurity concentration of the N + region 12 is implanted higher than the impurity concentration of the N well.
제2b도는 상기 산화막(11)을 제거한 후 전체면에 제1 BSG막(13)을 증착하고 급속열처리(Rapid Thermal Anneal)공정을 실시하여 상기 N+영역(12)의 상부에 P--층(20)이 형성된 상태의 단면도인데, 상기 P--층(20)은 상기 급속열처리공정시 제1 BSG막(13)으로부터 P--이온이 확산되어 형성되는 것이다.FIG. 2B shows that after removing the oxide film 11, the first BSG film 13 is deposited on the entire surface, and a rapid thermal annealing process is performed to form a P − layer on the N + region 12. 20 is a cross-sectional view of the formed state, wherein the P - layer 20 is formed by diffusion of P - ions from the first BSG film 13 during the rapid heat treatment process.
제2c도는 상기 제1 BSG막(13)을 제거한 후 게이트산화막(23) 및 폴리실리콘층을 순차적으로 형성하고 상기 폴리실리콘층에 P+형 불순물이온을 주입한 후 게이트전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막(23)을 순차적으로 패터닝하여 게이트전극(14)을 형성한 다음 상기 게이트전극(14)의 양측부에 산화막스페이서(16)를 형성한 상태의 단면도이다.2c is a photo using a mask for a gate electrode after removing the first BSG film 13, forming a gate oxide film 23 and a polysilicon layer in sequence, and implanting P + type impurity ions into the polysilicon layer ; The polysilicon layer and the gate oxide film 23 are sequentially patterned through an etching process to form a gate electrode 14, and then an oxide film spacer 16 is formed on both sides of the gate electrode 14. .
제2d도는 전체면에 제2 BSG막(15)을 증착한 후 P+형 불순물이온을 주입하여 접합영역(17)을 형성하고 급속열처리공정을 실시한 상태의 단면도인데, 이때 상기 P--층(20)내에 붕소(B)가 측면확산되어 상기 산화막스페이서(16)하부의 실리콘기판(10)에는 P-영역(18)이 형성된다. 또한 상기 P--층(20)에 의해 상기 게이트전극(14)내의 붕소(B)가 실리콘기판(10)으로 침투되는 것이 방지된다.2d the turning inde claim 2 BSG film 15 is a cross-sectional view of after deposition carried out a P + type impurity ion-implanted to the bonding region 17, the formation and rapid thermal process conditions for the whole area, in which the P - layer ( Boron (B) is laterally diffused into the silicon substrate 20 to form a P − region 18 in the silicon substrate 10 under the oxide spacer 16. In addition, the boron (B) in the gate electrode 14 is prevented from penetrating into the silicon substrate 10 by the P - layer 20.
제2e도는 상기 제2 BSG막(15)을 제거하므로써 P형 MOS 트랜지스터가 완성된 상태의 단면도이다.FIG. 2E is a cross-sectional view of the state in which the P-type MOS transistor is completed by removing the second BSG film 15. FIG.
제3a 내지 제3c도는 본 발명의 제2 실시예를 설명하기 위한 소자의 단면도로서,3A to 3C are cross-sectional views of devices for describing the second embodiment of the present invention.
제3a도는 실리콘기판(10)상에 산화막(21)을 성장시킨 후 N형 불순물이온을 주입하고 드라이브-인(Drive-In)하여 N웰(22)을 형성한 상태의 단면도이다.3A is a cross-sectional view of a state in which an N well 22 is formed by growing an oxide film 21 on a silicon substrate 10, implanting N-type impurity ions, and driving-in.
제3b도는 상기 산화막(21)을 제거한 후 전체면에 BSG막(19)을 증착하고 급속열처리공정을 실시하여 상기 N웰(22)의 상부에 P--층(24)이 형성된 상태의 단면도인데, 상기 P--층(24)은 상기 급속열처리공정시 BSG막(19)으로부터 P--이온이 확산되어 형성되는 것이다.3b is a cross-sectional view of the P - layer 24 formed on the N well 22 by removing the oxide film 21 and depositing the BSG film 19 on the entire surface and performing a rapid heat treatment process. the P-layer 24 is the rapid P from the heat treatment step when BSG film 19 - to which ions are diffused is formed.
제3c도는 상기 BSG막(19)을 제거한 후 게이트산화막(33) 및 폴리실리콘층을 순차적으로 형성하고 상기 폴리실리콘층에 P+형 불순물이온을 주입한 후 게이트전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막(33)을 순차적으로 패터닝하여 게이트전극(34)을 형성한 다음 상기 게이트전극(34)의 양측부에 산화막스페이서(26)를 형성하고 P+형 불순물이온을 주입하여 접합영역(27)을 형성한 후 열처리한 상태의 단면도인데, 이때 상기 P--층(24)내에 붕소(B)가 측면확산되어 상기 산화막스페이서(26) 하부의 실리콘기판(1)에는 P-영역(28)이 형성된다. 또한 상기 P--층(24)에 의해 상기 게이트전극(34)내의 붕소(B)가 실리콘기판(10)으로 침투되는 것이 방지된다.FIG. 3C is a photo-etching process using a gate electrode mask after removing the BSG film 19 and sequentially forming a gate oxide film 33 and a polysilicon layer, and implanting P + type impurity ions into the polysilicon layer. The polysilicon layer and the gate oxide layer 33 are sequentially patterned to form a gate electrode 34, and then oxide spacers 26 are formed at both sides of the gate electrode 34 to form P + type impurity ions. A cross-sectional view of the implanted region 27 after forming the junction region 27 is performed. The boron (B) is laterally diffused in the P - layer 24 to the silicon substrate 1 under the oxide spacer 26. P − region 28 is formed. In addition, the P − layer 24 prevents boron (B) in the gate electrode 34 from penetrating into the silicon substrate 10.
상술한 바와같이 본 발명에 의하면 실리콘기판에 N+영역을 형성하고 BSG막을 이용하여 상기 N+영역 상부에 P--층이 형성되도록 하므로써 얕은 접합깊이를 갖는 접합영역을 형성할 수 있으며 쇼트채널효과를 효과적으로 억제하고 높은 전달콘덕턴스를 이룰 수 있도록 하는 탁월한 효과가 있다.As described above, according to the present invention, a junction region having a shallow junction depth can be formed by forming an N + region on a silicon substrate and forming a P − layer on the N + region using a BSG film. It has an excellent effect of effectively suppressing and achieving high transfer conductance.
Claims (3)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006092A KR0146522B1 (en) | 1995-03-22 | 1995-03-22 | Transistor manufacturing method of semiconductor device |
| TW085103300A TW301035B (en) | 1995-03-22 | 1996-03-19 | Method of manufacturing a transistor in a semiconductor device |
| US08/621,731 US5681771A (en) | 1995-03-22 | 1996-03-21 | Method of manufacturing a LDD transistor in a semiconductor device |
| CN96105950A CN1077330C (en) | 1995-03-22 | 1996-03-22 | Method of manufacturing transistor in semiconductor device |
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| KR1019950006092A KR0146522B1 (en) | 1995-03-22 | 1995-03-22 | Transistor manufacturing method of semiconductor device |
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| KR960035912A KR960035912A (en) | 1996-10-28 |
| KR0146522B1 true KR0146522B1 (en) | 1998-11-02 |
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| KR1019950006092A KR0146522B1 (en) | 1995-03-22 | 1995-03-22 | Transistor manufacturing method of semiconductor device |
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| KR (1) | KR0146522B1 (en) |
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| TW388087B (en) * | 1997-11-20 | 2000-04-21 | Winbond Electronics Corp | Method of forming buried-channel P-type metal oxide semiconductor |
| US5880006A (en) * | 1998-05-22 | 1999-03-09 | Vlsi Technology, Inc. | Method for fabrication of a semiconductor device |
| US6274467B1 (en) | 1999-06-04 | 2001-08-14 | International Business Machines Corporation | Dual work function gate conductors with self-aligned insulating cap |
| US6927137B2 (en) * | 2003-12-01 | 2005-08-09 | Texas Instruments Incorporated | Forming a retrograde well in a transistor to enhance performance of the transistor |
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| JP3095564B2 (en) * | 1992-05-29 | 2000-10-03 | 株式会社東芝 | Semiconductor device and method of manufacturing semiconductor device |
| US5024959A (en) * | 1989-09-25 | 1991-06-18 | Motorola, Inc. | CMOS process using doped glass layer |
| JP3131436B2 (en) * | 1990-02-26 | 2001-01-31 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US5340770A (en) * | 1992-10-23 | 1994-08-23 | Ncr Corporation | Method of making a shallow junction by using first and second SOG layers |
| US5338698A (en) * | 1992-12-18 | 1994-08-16 | International Business Machines Corporation | Method of fabricating an ultra-short channel field effect transistor |
| JPH07297400A (en) * | 1994-03-01 | 1995-11-10 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device obtained thereby |
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| CN1077330C (en) | 2002-01-02 |
| CN1136709A (en) | 1996-11-27 |
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