KR0179069B1 - CMOS transistor manufacturing method - Google Patents
CMOS transistor manufacturing method Download PDFInfo
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- KR0179069B1 KR0179069B1 KR1019940007839A KR19940007839A KR0179069B1 KR 0179069 B1 KR0179069 B1 KR 0179069B1 KR 1019940007839 A KR1019940007839 A KR 1019940007839A KR 19940007839 A KR19940007839 A KR 19940007839A KR 0179069 B1 KR0179069 B1 KR 0179069B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000000873 masking effect Effects 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- -1 boron ions Chemical class 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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Abstract
본 발명은 씨모스 트랜지스터 제조방법에 관한 것으로 마스크공정을 줄임으로써 제조비용과 제조시간을 절감하고 실리콘벌크가 유기되지 않는 리트로그레이드 웰과 P+매몰층구조를 형성하므로써 소자특성을 향상시킬 수 있다.The present invention relates to a method of manufacturing a CMOS transistor, and by reducing the mask process, manufacturing cost and manufacturing time can be reduced, and the device characteristics can be improved by forming a retrode well and a P + buried layer structure in which silicon bulk is not organic.
이와 같은 발명은 제1도전형의 반도체기판상에 제1도전형웰과 제2 도전형웰 영역을 한정하여 제1, 제2 도전형웰영역 경계면에 필드산화막을 형성하는 제1공정, 상기 필드산화막 양측 기판상에 게이트 절연막과 게이트전극을 형성하는 제2공정, 상기 필드산화막 일측의 제1 도전형웰영역을 마스킹하여 타측에 제2도전형 이온주입으로 제2 도전형웰을 형성하는 제3공정, 상기 결과물 전면에 제1 도전형이온을 주입하여 상기 제2 도전형웰 일측 및 상기 제1 도전형웰영역에 제1 도전형웰을 형성함과 동시에 제1, 제2 도전형웰 하측에 제1 도전형 매몰층을 형성하는 제4공정, 상기 제2 도전형웰의 게이트전극 양측에서 제1 도전형 소오스 및 드레인영역을 형성하여 제1도전형 트랜지스터를 형성하는 제5공정, 상기 제1 도전형웰의 게이트전극 양측에 제2 도전형 소오스 및 드레인영역을 형성하여 제2 도전형 트랜지스터를 형성하는 제6 공정을 포함하여 이루어짐을 특징으로하는 씨모스 트랜지스터 제조방법이다.This invention is a first step of forming a field oxide film on the interface between first and second conductive well regions by defining a first conductive well and a second conductive well region on a semiconductor substrate of a first conductivity type. A second step of forming a gate insulating film and a gate electrode on the third step; a third step of forming a second conductive well by masking a first conductive well region on one side of the field oxide film and implanting a second conductive ion on the other side; Implanting a first conductivity type ion into the first conductivity type well at one side of the second conductivity type well region and the first conductivity type well region to form a first conductivity type buried layer below the first and second conductivity type wells A fourth step of forming a first conductive transistor by forming a first conductive source and a drain region on both sides of a gate electrode of the second conductive well, and a second conductive on both sides of the gate electrode of the first conductive well Brother A sixth step characterized in that the method for producing the CMOS transistor yirueojim, including forming a second conductivity type to form a transistor switch and a drain region.
Description
제1도는 종래 기술에 위한 씨모스 트랜지스터 제조방법을 도시한 공정순서도.1 is a process flowchart showing a CMOS transistor manufacturing method according to the prior art.
제2도는 본 발명에 의한 씨모스 트랜지스터 제조방법을 도시한 공정순서도.2 is a process flowchart showing a CMOS transistor manufacturing method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : P형 실리콘기판 11 : 산화막10: P-type silicon substrate 11: oxide film
12 : 필드 산화막 13 : 게이트12: field oxide film 13: gate
14a : 제1 감광막 14b : 제2 감광막14a: 1st photosensitive film 14b: 2nd photosensitive film
15a : 제1 질화막측벽 15b : 제2 질화막측벽15a: first nitride film side wall 15b: second nitride film side wall
본 발명은 높은 에너지로 이온주입 공정을 실시한 씨모스 트랜지스터 제조 방법에 관한 것으로 특히 마스크공정 단계를 줄여서 제조비용과 제조시간을 절감하고 소자특성의 향상에 적당하도록 한 씨모스 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing CMOS transistors having a high energy ion implantation process, and more particularly to a method for manufacturing CMOS transistors by reducing the mask process step to reduce manufacturing cost and manufacturing time and to improve device characteristics.
종래 기술에 의한 씨모스 트랜지스터 제조방법을 제1도를 참조하여 설명하면 다음과 같다.The CMOS transistor manufacturing method according to the prior art will be described with reference to FIG.
먼저 제1도 (a)와 같이 P형 실리콘기판(1)상에 제1산화막(2), 질화막(3), 감광막(4)을 차례로 증착한다.First, as shown in FIG. 1A, the first oxide film 2, the nitride film 3, and the photosensitive film 4 are sequentially deposited on the P-type silicon substrate 1.
이어서, 제1도(b)와 같이 N-well이 형성될 영역을 상기 감광막(4)으로 정의한 후, 감광막을 마스크로 이용한 식각공정으로 상기 질화막(3)을 선택적으로 제거하고, 마스크로 사용한 상기 감광막을 제거한다.Subsequently, as shown in FIG. 1 (b), the region in which the N-well is to be formed is defined as the photosensitive film 4, and then the nitride film 3 is selectively removed by an etching process using the photosensitive film as a mask. Remove the photoresist.
그리고 N-well이 형성될 영역에 P(Phosphorus)이온을 주입한다.P (Phosphorus) ions are implanted into the region where the N-well is to be formed.
이어서 제1도 (c)와 같이 상기 결과물을 O2분위기에서 열처리하여 제1 필드산화막(5)과 N-well을 형성한다.Subsequently, as shown in FIG. 1C, the resultant is heat-treated in an O 2 atmosphere to form a first field oxide film 5 and an N-well.
그리고, 상기 제1 필드산화막(5)을 마스크로 이용한 식각공정으로 상기 질화막(3a)을 제거한 후, P-well이 형성될 영역에 보론(Boron)이온을 주입한다.After the nitride film 3a is removed by an etching process using the first field oxide film 5 as a mask, boron ions are implanted into a region where a P-well is to be formed.
이어서 제1도 (d)와 같이 상기 결과물을 열처리하고 드라이브-인 확산으로 인해 P-well을 형성하고 상기 제1 필드산화막(5)과 제1 산화막(2)을 식각공정으로 제거한다.Subsequently, as shown in (d) of FIG. 1, the resultant is heat-treated to form a P-well due to drive-in diffusion, and the first field oxide film 5 and the first oxide film 2 are removed by an etching process.
이어서 제1도 (e)와 같이 전면에 제2 산화막(6)과 질화막(도시하지 않음)을 증착하고 N-well과 P-well의 경계면영역의 상기 질화막을 선택적으로 제거한다.Subsequently, as shown in FIG. 1E, a second oxide film 6 and a nitride film (not shown) are deposited on the entire surface, and the nitride film in the interface region between the N-well and the P-well is selectively removed.
그리고 O2분위기에서 열처리하여 제2 필드산화막(7)을 형성한 후 상기 질화막을 식각공정으로 제거한다.After the heat treatment in an O 2 atmosphere to form a second field oxide film 7, the nitride film is removed by an etching process.
이어서 제1도 (f)와 같이 상기 P-well 영역에 마스크(도시하지 않음)를 패턴닝하여 N-well 영역에 문턱전압(VTN)을 주입하고 상기 마스크를 제거한 다음, 반대로 N-well 영역에 마스크(도시하지 않음)를 패턴닝하여 P-well 영역에 문턱전압(VTP)을 주입하고 상기 마스크를 제거한다.Subsequently, as shown in FIG. 1 (f), a mask (not shown) is patterned in the P-well region to inject a threshold voltage V TN into the N-well region, and the mask is removed. A mask (not shown) is patterned in to inject a threshold voltage V TP into the P-well region, and the mask is removed.
이어서 상기 액티브영역(N-well 및 P-well 각각)에 게이트(8)을 선택적으로 형성한 후, P-well 영역에 마스크(도시하지 않음)를 패턴닝하여 N-well 영역에 P-이온을 주입하고 상기 마스크를 제거한 다음 반대로, N-well 영역에 마스크(도시하지 않음)를 패턴닝하여 P-well 영역에 N-이온을 주입하고 상기 마스크를 제거한다.Ions - then said active region (N-well and P-well, respectively) P in the N-well area, after selectively forming the gate 8, by patterning a mask (not shown) in the P-well region in After implanting and removing the mask, on the contrary, a mask (not shown) is patterned in the N-well region to inject N - ions into the P-well region and the mask is removed.
이어서 제1도 (g)와 같이 전면에 절연막을 증착하고 건식식각으로 상기 게이트(8) 측면에 절연막측벽(9)를 형성한다.Subsequently, as shown in FIG. 1 (g), an insulating film is deposited on the entire surface and an insulating film side wall 9 is formed on the side of the gate 8 by dry etching.
이후에 P-well 영역에 마스크(도시하지 않음)를 패턴닝하여 N-well 영역에 P+이온을 주입하고 상기 마스크를 제거한 다음 반대로 N-well 영역에 마스크(도시하지 않음)를 패턴닝하여 P-well 영역에 N+이온을 주입하고, 상기 마스크를 제거하면 LDD(Lightly Doped Drain)구조의 소오스, 드레인영역을 포함한 종래의 씨모스를 완성한다.Subsequently, a mask (not shown) is patterned in the P-well region to implant P + ions into the N-well region, the mask is removed, and then a mask (not shown) is patterned in the N-well region. Injecting N + ions into the -well region and removing the mask completes the conventional CMOS including the source and drain regions of the LDD (Lightly Doped Drain) structure.
그러나, 이상에서 상술한 씨모스 트랜지스터 제조방법은 제조공정시 여러 단계의 마스크공정을 거쳐야 하므로 제조비용과 제조시간의 부담이 있었고 well을 형성할 때 행해지는 열처리의 드라이브-인 확산 공정시 실리콘벌크가 유기되는 문제점이 있었다.However, since the CMOS transistor manufacturing method described above has to undergo several steps of masking in the manufacturing process, there is a burden of manufacturing cost and manufacturing time, and silicon bulk is produced during the drive-in diffusion process of heat treatment performed when forming wells. There was an issue being abandoned.
본 발명은 상술한 문제점을 해결하기 위하여 안출한 것으로 높은 에너지를 사용하여 이온주입을 함으로써 씨모스 제조공정시 필요로 하는 여러 단계의 마스크공정을 줄이고 제조시간, 제조비용을 절감할 뿐 아니라 실리콘벌크가 유기되지 않는 씨모스 트랜지스터의 제조방법을 제공하는 데 그 목적이 있다.The present invention has been made in order to solve the above-mentioned problems, by ion implantation using high energy to reduce the mask process of the various steps required in the CMOS manufacturing process and to reduce the manufacturing time, manufacturing cost as well as silicon bulk It is an object of the present invention to provide a method for manufacturing a CMOS transistor that is not organic.
상기 목적을 달성하기 위한 본 발명의 씨모스 트랜지스터 제조방법은 제1 도전형의 반도체기판상에 제1 도전형웰과 제2 도전형웰 영역을 한정하여 제1, 제2 도전형웰영역 경계면에 필드산화막을 형성하는 제1 공정, 상기 필드산화막 양측 기판상에 게이트 절연막과 게이트전극을 형성하는 제2 공정, 상기 필드산화막 일측의 제1 도전형웰영역을 마스킹하여 타측에 제2 도전형 이온주입으로 제2 도전형웰을 형성하는 제3 공정, 상기 결과물 전면에 제1 도전형이온을 주입하여 상기 제2 도전형웰 일측 및 상기 제1 도전형 웰영역에 제1 도전형웰을 형성함과 동시에 제1, 제2 도전형웰 하측에 제1 도전형 매몰층을 형성하는 제4공정, 상기 제2 도전형웰의 게이트전극 양측에 제1 도전형 소오스 및 드레인영역을 형성하여 제1 도전형 트랜지스터를 형성하는 제5공정, 상기 제1 도전형웰의 게이트전극 양측에 제2 도전형 소오스 및 드레인영역을 형성하여 제2 도전형 트랜지스터를 형성하는 제6공정을 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, the CMOS transistor fabrication method of the present invention defines a first conductive well and a second conductive well region on a first conductive semiconductor substrate and forms a field oxide film on the interface of the first and second conductive well regions. A first step of forming, a second step of forming a gate insulating film and a gate electrode on both sides of the field oxide film, and a second conductivity type ion implantation on the other side by masking a first conductive well region on one side of the field oxide film In the third step of forming a mold well, first conductive type ions are injected into the entire surface of the resultant to form first conductive wells on one side of the second conductive well and the first conductive well region, A fourth step of forming a first conductive buried layer under the mold well, a fifth step of forming a first conductive transistor by forming first conductive source and drain regions on both sides of the gate electrode of the second conductive well, And a sixth step of forming a second conductive transistor by forming second conductive source and drain regions on both sides of the gate electrode of the first conductive well.
이하, 첨부된 제2도를 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the attached FIG. 2.
먼저 제2도 (a)와 같이 P형 실리콘기판(10)상에 산화막(11)과 질화막(도시하지 않음)을 차례로 증착하고 필드산화막이 형성될 영역(N-well과 P-well의 경계영역)의 질화막을 선택적으로 제거한다.First, as shown in FIG. 2A, an oxide film 11 and a nitride film (not shown) are sequentially deposited on the P-type silicon substrate 10, and the region where the field oxide film is to be formed (the boundary region between the N-well and the P-well). ) Is selectively removed.
이후, O2분위기에서 열처리하여 필드산화막(12)을 형성하고 상기 질화막을 제거한다.Thereafter, heat treatment is performed in an O 2 atmosphere to form a field oxide film 12 and the nitride film is removed.
이어서, 제2도 (b)와 같이 상기 액티브영역(형성될 N-well 및 P-well 각각)에 선택적으로 게이트(13)를 형성하고, N-well의 형성을 위해 P-well이 형성될 영역에 제1 감광막(14a)을 패턴닝한다.Subsequently, as shown in FIG. 2 (b), the gate 13 is selectively formed in the active region (each of the N-well and P-well to be formed), and the region where the P-well is to be formed to form the N-well. The first photosensitive film 14a is patterned.
다음에 상기 제1 감광막(14a)을 마스크를 이용하여 인(Phosphorus)이온을 주입하고 열처리를 통한 드라이브-인 확산으로 N-well을 형성한다.Next, Phosphorus ions are implanted into the first photoresist layer 14a using a mask, and N-wells are formed by drive-in diffusion through heat treatment.
이어서 제2도(c)와 같이 전면에 상기 인 이온을 주입할 때 비해 상대적으로 높은 에너지의 보론이온을 주입하여 제1 감광막(14a) 하측에 P-well을 형성함과 동시에 상기 N-well 및 P-well 영역하측에 P+매몰층을 동시에 형성한다.Subsequently, as shown in FIG. 2C, boron ions having a relatively high energy are implanted to form P-wells below the first photoresist layer 14a as compared with when the phosphorus ions are injected to the front surface. P + buried layer is formed simultaneously under the P-well region.
이 때의 공정은 인이온을 주입할 때 보다 높은 에너지로 보론을 주입하여 이온주입깊이가 깊어지고, P-well과 P+매몰층의 구분은 제1 감광막(14a)이 있는 부분에서는 이온주입 농도차가 발생하기 때문에 동시에 형성할 수 있다.In this process, the ion implantation depth is deepened by injecting boron at a higher energy when phosphorus ions are injected, and the division of P-well and P + buried layer is ion implantation concentration at the portion where the first photosensitive film 14a is present. Since a difference arises, it can form simultaneously.
이어서 제2도 (d)와 같이 전면에 질화막(도시하지 않음)을 증착하고 이방성 식각하여 N-well 상측의 게이트측면에 제1 질화막측벽(15a)을 형성한다.Subsequently, a nitride film (not shown) is deposited on the entire surface and anisotropically etched as shown in FIG. 2D to form the first nitride film side wall 15a on the gate side of the N-well.
그리고, 상기 제1 감광막(14a)을 마스크로 이용하여 N-well 영역에 P+이온으로 BF2이온을 주입하고, P-이온은 틸트(Tilt) 또는 로테이션(Rotation) 공정으로 주입한다.Then, using the first photoresist layer 14a as a mask, BF 2 ions are implanted into the N-well region as P + ions, and P − ions are implanted by a tilt or rotation process.
이어서 제2도 (e)와 같이 상기 제1 감광막(14a)을 제거하고 N-well 영역에 제2 감광막(14b)을 패턴닝한 후, 전면에 질화막(도시하지 않음)을 증착하고 이방성 식각으로 P-well 상측의 게이트측면에 제2 질화막측벽(15b)을 형성한다.Subsequently, as shown in FIG. 2E, the first photoresist film 14a is removed, and the second photoresist film 14b is patterned in the N-well region, and then a nitride film (not shown) is deposited on the entire surface. The second nitride film side wall 15b is formed on the gate side of the P-well.
이어서 제2도 (f)와 같이 상기 제2 감광막(14b)을 마스크로 이용하여 P-well 영역에 N+이온으로 비소이온을 주입하고, N-이온은 틸트, 로테이션 공정으로 주입하여 소오스와 드레인영역을 완성한다.Subsequently, as shown in FIG. 2 (f), arsenic ions are implanted with N + ions into the P-well region using the second photoresist film 14b as a mask, and N - ions are implanted with a tilt and rotation process to supply a source and a drain. Complete the area.
이어서 제2도 (g)와 같이 N-well 영역에 마스크로 사용된 상기 제2 감광막(14b)를 제거하면 완성된 씨모스 트랜지스터가 형성된다.Subsequently, as shown in FIG. 2G, when the second photosensitive layer 14b used as a mask is removed in the N-well region, a completed CMOS transistor is formed.
이상에서 상술한 바와 같이 본 발명의 씨모스 트랜지스터 제조방법에 있어서는 마스크공정을 줄임으로써 제조비용과 제조시간을 절감할 뿐 아니라 실리콘벌크가 유기되지 않는 리트로그레이드 웰(Retrograde Well)과 P+매몰층구조를 형성함으로써 소자특성이 향상되는 효과가 있다.As described above, in the CMOS transistor manufacturing method of the present invention, the manufacturing process and manufacturing time can be reduced by reducing the mask process, and the retrograde well and the P + buried layer structure in which silicon bulk is not induced. Formation of the device has the effect of improving the device characteristics.
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| KR1019940007839A KR0179069B1 (en) | 1994-04-14 | 1994-04-14 | CMOS transistor manufacturing method |
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