JPS645322B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device, and more particularly to a sequence control device suitable for dealing with abnormal situations occurring during sequence control operations and performing good time-limited program control.

In a sequence control device that temporally controls controlled equipment to advance processes sequentially, when an abnormal situation occurs in the system including the control device while executing a certain process, conventional methods have been used to detect the abnormality. Based on this, the control is immediately stopped and, at the same time, both the process selection signal and the time limit signal are returned to their initial states.

Therefore, when the system returns to normal state, if the process selection signal of the sequence control device is returned to the signal immediately before stopping and restarted, the sequence control device will restart the process from the beginning. In addition to wasting the time required to return to the state immediately before the stoppage, some systems have drawbacks such as over-controlling the process and causing undesirable situations.

Therefore, in order to avoid such a situation, when an abnormality occurs in the system, the process signal and time signal at that time are retained, and when the system recovers to normal state, the sequence control device is restarted from the state immediately before stopping. A method was proposed to restart the .

According to this method, if the abnormality occurring in the system is caused by the sequence control device,
There is no need for wasted control, and sequence control can be performed continuously very conveniently.

However, if the abnormality is caused by the process, an inconvenient situation may occur.

In other words, in the case of a device error, the process side will stop immediately when the sequence control device stops, and when restarted, both the control device and process side will be restarted from the state immediately before the stop, so no particular problem will occur. .

However, when an abnormality occurs on the process side, such as when a part of a pipe is blocked and fluid stops flowing, the abnormality is usually not detected immediately and is detected only after a certain amount of time has passed. Often detected.

As a result, there is a discrepancy between the stop states on the control device side and the process side, and when the sequence control device is restarted from the state immediately before it was stopped in the same way as in the case of an abnormality on the device side, the processing time for the process in that step is insufficient, A situation occurred where processing was incomplete.

In view of the above points, the present invention provides that even if an abnormality occurs in the system during the sequence control operation and the sequence control is interrupted, when the system returns to the normal state, the It is an object of the present invention to provide a sequence control device that can continue executing the remaining processing.

In order to achieve this object, the present invention restarts the sequence control device from the process processing state immediately before the abnormality occurs when an abnormality occurs on the control device side, and restarts the sequence control device from the process processing state immediately before the abnormality occurs when the abnormality occurs on the process side. The feature is that it is configured to restart from the beginning.

Hereinafter, the present invention will be explained with reference to the embodiments shown in the figures.

FIG. 1 is a schematic configuration diagram of a sequence control device showing one embodiment of the present invention, and 1 is a sequence controller.

This sequence controller 1 includes a calculation section 2 that performs sequence calculations, an input section 3 that inputs input conditions etc. from the outside, and an output section 4 that outputs calculation results to the outside.
It consists of

5A is a power supply for the calculation section 2, 5B is a power supply necessary for inputting an external input signal to the input section 3, and 5C is a power supply necessary for the output section 4 to drive the controlled device 6.

These power supplies 5A to 5C have different usage patterns, so they are separate power supplies, but by using a common power supply and using power supply dividing fuses 7A to 7C or wiring circuit breakers (MCCB),
The common power source may be divided and then supplied to each part.

8A to 8C are monitoring relays for monitoring each power source 5A to 5C, and a contact 2a provided in the calculation section 2 is a contact for detecting a failure of the sequence controller 1, and a contact is provided on the input side of the input section 3. The operating contact 9-b of the controlled device 6 is the b contact of the control device abnormality detection relay 9, which will be described later.
0 is a process abnormality reset switch, and 11 is a process selection switch.

Although not shown in the figure, there are many controlled devices, their operating contacts, and process selection switches, and they are connected in the same way as shown.

FIG. 2 shows a hold/reset circuit for a sequence controller abnormality signal.

In the case of this embodiment, the abnormalities on the sequence control device side include failures in the sequence controller 1 and abnormalities in each of the power supplies 5A to 5C.

Therefore, failure detection contact 2a, monitoring relay 8A
B contacts 8A-b to 8C-b of ~8B are connected to the control device abnormality detection relay 9, and when one of these contacts closes, the relay 9 operates and its A contact 9
-a is configured to be self-maintained. Further, the self-holding is released by opening the control device abnormality reset switch 12.

That is, the circuit shown in FIG. 2 is a circuit that monitors the status of the sequence control device and outputs a sequence control device normal signal if it is normal, and outputs a sequence control device abnormality signal if an abnormality occurs.

Note that the power source 5D in FIG. 2 is the same as the power source 5A in FIG.
A different power source is used to ensure survival in the event of loss of 5C.

FIG. 3 is a partial block diagram of the arithmetic unit 2 of FIG. 1, particularly showing the n-step and the sequence arithmetic circuits before and after it.

Since the arithmetic circuits in each process are configured in the same way, the explanation will be given for the n process.

O1 to O3 are OR circuits, A1 to A4 are AND circuits, N1 to N3 are NOT circuits, R1 and R2 are latch circuits, and T is a timer.

The OR circuit O1 has a process selection signal 1 that is output from the (n-1) side when the (n-1) process is completed.
3 and a manual process selection signal 14 generated when the process selection switch 11 of FIG. 1 is pressed. These process selection signals are OR circuit O1
It is held by the feedback loop to and latched by the latch circuit R1.

This latch circuit R1 is configured so that even if the calculation power supply 5A is lost, it stores the signal input immediately before the loss.

A process abnormality signal 15, which is generated when the process side becomes abnormal, is input to the OR circuit O2. This signal 15 is also held by the feedback loop to the OR circuit O2 as described above, and is also held by the latch circuit R2.
It is latched by.

In order to release the process abnormality signal 15 from being held, the process abnormality reset signal 16 generated when the switch 10 in FIG. 1 is pressed is input to the AND circuit A2 via the NOT circuit N2.

That is, by generating this signal 16, the signal input from the NOT circuit N2 to the AND circuit A2 becomes logic "0", and as a result, the signal 15 is no longer held as a result of being fed back to the OR circuit O2.

In other words, a circuit 18 consisting of an OR circuit O2, a latch circuit R2, an AND circuit A2, and a NOT circuit N2.
is a circuit that outputs a process abnormality signal when an abnormality occurs on the process side, and maintains that state until the process side returns to normal and is set by switch 10 in FIG.

The output of this circuit is OR circuit O3, NOT circuit N
1 to the AND circuit A1.

Therefore, the holding of the process selection signal 13 or 14 is released by the generation of the process abnormality signal.

In other words, a circuit 18 consisting of an OR circuit O1, an AND circuit A1, a latch circuit R1, and a NOT circuit N1.
When the process is selected, outputs a process selection signal and holds that state, but releases the holding when the process abnormality signal 15 occurs,
This circuit outputs a process non-selection signal, that is, logic "0".

The sequence control device normal signal 19 generated when the relay 9 in FIG. 2 is not operating and the output of the circuit 18 are input to the AND circuit A3.

The timer T performs a clock count when there is an output from the AND circuit A3, and when it has counted a preset value, it ends the process and outputs a process selection signal for selecting the next (n+1) process. This timer T immediately stops its operation when the output from the AND circuit A3 disappears. Furthermore,
When a process non-selection signal is input from the circuit 18 via the NOT circuit N3, the count value is reset to the initial state.

That is, the circuit 20 consisting of the AND circuit A3, the timer T, and the NOT circuit N3 is enabled to operate by the process selection signal, starts timed operation by the generation of the sequence control device normal signal 19, and selects the next process after a predetermined time period. This circuit outputs a signal to indicate the sequence control device, while stopping the timed operation by outputting a sequence control device abnormality signal, and is reset to the initial state by outputting a process non-selection signal.

The process selection signal outputted from the circuit 18 and the sequence control device normal signal 19 are input to the equipment operation command unit 20 via the AND circuit A4, and the contact 4a of the output unit 4 in FIG. make it work.

Furthermore, when the next n+1 process is selected, the next process selection signal 22 is input to the OR circuit O3 in order to release the holding of its own process selection signal.

The circuit shown in FIG. 3 described above may be configured as hardware, but as microcomputers have advanced recently and high-performance devices have become available at low cost, in this embodiment, the circuit shown in FIG. The arithmetic unit 2 is constructed using a microprocessor, and therefore, all of the circuit configurations described above are constructed using software.

The sequence control device of this embodiment is configured as described above, and if both the sequence control device side and the process side are in a normal state, the n-process selection signal 13 or the intermediate process is skipped when the time of the n-1 process ends. If it is desired to execute n steps, a manual step selection signal 14 is input.

The circuit 18 holds this signal and simultaneously outputs it to the AND circuits A3 and A4.

At this time, the sequence control device normal signal 19 is also input to the AND circuits A3 and A4.

Therefore, the device operation command section 21 operates, the contact 4a of the output section 4 closes, and the controlled device 6 starts up.
At the same time, the timer T starts its time-limited operation.

When the time required to execute n steps has elapsed, timer T times up and outputs a signal to select the next (n+1) step.

As a result, the n+1 process immediately starts operating in the same manner as described above. Then, the process selection signal 2
2 is input to the OR circuit O3 of the n process, and the holding of the process selection signal in the circuit 18 is released.

As a result, the circuit 18 outputs a process non-selection signal, stops the operation of the controlled equipment 6, and resets the timer T.

During normal operation, each step is performed in sequence at predetermined intervals in this way, but if the above-mentioned abnormality occurs on the sequence control device side during execution of this sequence control operation, the sequence control is started from the circuit shown in Figure 2. A device error signal is generated. That is, the control device normal signal 19 becomes logic "0".

As a result, the AND circuit A3 is closed, its output becomes logic "0", and the operation of the timer T is stopped.
At the same time, the AND circuit A4 closes and the controlled device 6 also stops operating.

At this time, the circuit 18 holds the process selection signal,
Even if the calculation power supply 5A is lost, the signal input to the timer T via the NOT circuit N3 will never become logic "1", so the timer T
simply stops working and is never reset.

Eventually, when the abnormality in the sequence control device is removed and the reset switch 12 in FIG. 2 is pressed, the sequence control device normal signal 19 is again input to the AND circuits A3 and A4.

At this time, the circuit 18 holds the process selection signal and stores it in the latch circuit R1 even if the calculation power supply 5A is lost.

Therefore, simultaneously with the input of the sequence control device normal signal 19, the AND circuits A3 and A4 open, the controlled device 6 and the timer T operate again, and the remaining sequence control is executed.

Next, when an abnormality occurs on the process side, a process abnormality signal 15 is input to the circuit 17 and held.

In response to this process abnormality signal, the circuit 18 releases the holding of the process selection signal and outputs a process non-selection signal.

As a result, the AND circuits A3 and A4 are closed, and the operation of the timer T and the controlled device 6 is stopped. At the same time, the signal input to the timer T via the NOT circuit N3 is set to logic "1". Reset.

Eventually, the abnormality on the process side will be removed and the first
When the reset switch 10 shown in the figure is pressed, a process abnormality reset signal 16 is input to the circuit 17, and the holding of the process abnormality signal in the circuit 17 is released.

Restarting after recovery from a process abnormality is performed by manually generating a process signal 14 by pressing the process selection switch shown in FIG.

As a result, the timer T operates again from the initial state, and the abnormally processed n process is newly processed from the beginning. At this time, if the detection of the abnormal state on the process side is delayed and the previous n-1 process has also been abnormally processed, pressing the switch for selecting the n-1 process enables that process.

When an abnormality occurs on the process side in this way, restarting after recovery must be performed after ascertaining the state of the process, unlike in the case of a control device abnormality, so in this example, such a restart is performed. It is possible. However, if there is no need for this and it is desired to automatically start sequence control from the process at the time it was stopped, it is possible to do so by inputting the process abnormality reset signal 16 to the OR circuit O1.

In the above embodiments, failures in each of the power supplies 5A to 5C and failures in the sequence controller 1 have been explained as examples of abnormalities on the sequence control device side, but the present invention is not limited to this, and the present invention is not limited to this, but may be caused by failures in controlled equipment, for example. It goes without saying that device abnormalities other than process abnormalities, such as the above, can be treated as abnormalities on the sequence control device side and handled in the same manner as in the above embodiments.

As described above, according to the present invention, restart is performed by distinguishing between device abnormality and process abnormality, so even if an abnormality occurs, after recovery, good sequence control that deals with it can be continued. be able to.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a sequence control device showing an embodiment of the present invention, FIG. 2 is a sequence control device abnormal signal hold/reset circuit in the sequence control device, and FIG. 3 is a sequence controller operation of FIG. 1. FIG. 1... Sequence controller, 2... Arithmetic unit, 2a... Sequence controller failure contact,
3...Input section, 4...Output section, 4a...Output contact, 5A to 5D...Power source, 6...Controlled device, 6
a...Operating contacts of controlled equipment, 7A-7C...Fuses, 8A-8C...Monitoring relays, 8A-b...
8C-b...B contact of the monitoring relay, 9...Control device abnormality detection relay, 9-a...A contact of the control device abnormality detection relay, 9-b...B contact of the control device abnormality detection relay, 10... . . . Process abnormality reset switch, 11 . . . Process selection switch, 12 . . . Control device abnormality reset switch.

Claims (1)

[Claims] 1. In a sequence control device that sequentially controls controlled devices over time, the device normally generates a normal signal, but when an abnormality occurs on the sequence control device side,
means for generating an equipment abnormality signal and holding the state until reset; means for generating a process abnormality signal and holding the state until reset when an abnormality occurs on the process side; means for generating a process selection signal when the process selection signal is selected and holding the state, and releasing the holding state when the process abnormality signal is generated to generate a process non-selection signal; Furthermore, when the device normal signal is generated, the timed operation is started, and a signal to select the next process after a predetermined time period is generated, while the timed operation is stopped when the device abnormality signal is generated, and the process non-selection signal is generated. 1. A sequence control device comprising: a timer for returning to an initial state upon occurrence of the above; and a means for operating the controlled equipment in accordance with the process selection signal and the device normal signal.