JPS62123531A - Cpu supervisory unit - Google Patents

Abstract

PURPOSE:To recognize immediately the interruption of the clocks for actuation of a watchdog timer by using a timer for monitor of a watchdog timer which is reset by the clocks for actuation of the watchdog timer. CONSTITUTION:A timer 8 for monitor of watchdog timer is actuated by a system clock 7 for control of peripheral device obtained from a CPU 3 and then reset by a clock 5 for actuation of a watchdog timer. Then the time-up signal of the timer 8 is used as a trouble signal for watchdog timer. Thus the timer 8 is never reset in case a watchdog timer circuit 2 has a trouble owing to the interruption of the clock 5 that is caused by some abnormality of the CPU 3. Then the timer 8 has a time-up state and produces the trouble signal of the circuit 2. Thus it is possible to detect completely not only the abnormality of the CPU 3 but the abnormality of the circuit 2 itself. Then a measure is possible as desired.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a device for monitoring abnormal operation caused by a hardware failure or the like of a CPU.

(Summary of the Invention) The present invention provides a CPU monitoring device equipped with a watchdog timer for monitoring abnormalities in the operation of the CPU, which is also capable of monitoring failures in the watchdog timer itself.

(Prior art and its problems) FIG. 2 shows an example of a conventional CPU monitoring device.

In the figure, 1 is a clock generation circuit, 2 is a watchdog timer circuit, 3 is a CPU, and 4 is a control board for resetting the watchdog timer circuit 2.

The clock circuit 1 outputs a clock 5°6 for the 2nd series gun. These clocks 5 and 6 are extremely independent so that even if one clock is interrupted, the other clock will not be interrupted at the same time.

A reset command for resetting the watchdog timer circuit 2 via the control board 4 is inserted into the program of the CPU 3.

Therefore, if the CPU 3 is normal in terms of hardware, the dog timer circuit that operates with the clock 5 is always reset via the control board 4 before time-up, so that no CPU operation abnormality signal is generated.

On the other hand, if the CPU 3 has a hardware failure, for example, the watchdog timer circuit 2 will not be reset, and after a certain period of time, the watchdog timer circuit 2 will time out and issue a CPU malfunction signal. It will be done.

Note that the frequency of the clock 5 is set to, for example, 250KH2, and the frequency of the clock 6 is set to about 4MH2.

However, in such a CPU monitoring device, the CPU
Although it functions effectively against hardware abnormalities on the a side, the clock 5 that should operate the watchdog timer circuit 2
There is a problem that if the system itself is interrupted, it cannot function effectively at all.

(Objective of the Invention) The object of the invention is to enable a CPU monitoring device of this type to immediately recognize when the clock 5 for operating the watchdog timer circuit 2 is interrupted. It is in.

(Structure and Effects of the Invention) In order to achieve the above object, the present invention provides a clock timer that operates with a clock independent of the CPU and is reset by a reset instruction inserted into the program of the CPU; The present invention is characterized by comprising: a timer for monitoring a watchdog timer that operates with the obtained system clock for controlling peripheral devices and is reset with a clock for operating the watchdog timer.

With such a configuration, it is possible to reliably detect not only when the CPU malfunctions but also when the watchdog timer malfunctions, and based on this, necessary measures such as stopping the CPU operation can be taken. Can be taken immediately.

Furthermore, since the system clock for peripheral device control obtained from the CPU is used, the performance of this type of monitoring device can be improved without requiring any major changes in hardware.

(Description of Embodiments) FIG. 1 is a block diagram showing the electrical configuration of an apparatus according to an embodiment of the present invention. In addition, in the figure, the same reference numerals are given to the same components as those of the conventional example, and the description thereof will be omitted.

As shown in the figure, the feature of the CPU monitoring device according to the present invention is that it operates with a system clock 7 for controlling peripheral devices obtained from the CPU 3, and monitors a watchdog timer that is reset with a clock 5 for operating the watchdog timer. A timer 8 is provided for this purpose, and the time-up signal of this timer is used as a watchdog timer failure signal.

Note that in this example, the watchdog timer monitoring timer 8
A bidirectional differentiator circuit 9 is inserted before the reset input Re5et, so that the watchdog timer monitoring timer 8 is restarted even if the clock 5 is interrupted at either "H" or "L". .In addition, Re5et is a terminal that is reset by "", and from the bidirectional differentiator circuit 9 "
It is assumed that a 'shi' pulse is output.

Further, as a microprocessor constituting the CPU 3, for example, a Motorola 6809 is used, and a clock 6809 is used.
EXTAL as system clock 7, and E as system clock 7.
You can use

According to the above configuration, as long as the CPU 3 is normal, the watchdog timer circuit 2 is reset periodically.
A CPU operation abnormality signal is never issued.

On the other hand, if some abnormality occurs in the CPU 3 and the watchdog timer circuit 2 is not reset, then
When the timer circuit 2 times out, a CPU operation abnormality signal is generated.

This CPU operation abnormality signal is normally supplied to the reset input of the CPU 3, thereby stopping the operation of the CPU 3.

Next, regarding the operation of the main part of the present invention, the differential circuit 9 supplies a very small width ``bi'' pulse in response to both the rising edge and the falling edge of the clock 5. The timer 8 for monitoring the A spot dog timer is repeatedly reset.

Therefore, if the watchdog timer circuit 2 breaks down due to interruption of the clock 5, the continuous dog timer monitoring timer 8 is no longer reset, and when it times up, a watchdog timer failure signal is generated.

In this case, for example, the watchdog timer failure signal
It is possible to interrupt the PU3 and take appropriate troubleshooting measures.

In this way, in this embodiment, not only an abnormality occurs in the CPU 3, but also an abnormality occurring in the watchdog timer circuit itself that monitors CPU@ is reliably detected, and based on this, necessary information for the CPU 3 is detected. Measures can be taken immediately.

Moreover, the configuration for this purpose uses the system clock conventionally used in the CPU and only requires adding a separate timer to it, without causing a significant increase in cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the electrical configuration of a CPU monitoring device according to the present invention, and FIG. 2 is a block diagram showing the configuration of the conventional device. 1...Clock circuit 2...Watchdog timer circuit 3...CPU 4...Control port 5...Watchdog timer operation clock 6...C
PU operation clock 7...System clock 8/...Watchdog timer monitoring timer 9...Bidirectional differentiation circuit

Claims (1)

[Claims] (1) Operates with a clock independent of the CPU, and
A watchdog timer that is reset by a reset instruction inserted into the U program, and a watchdog timer that operates using the system clock for controlling peripheral devices obtained from the CPU and that is reset by the clock for operating the watchdog timer. A CPU monitoring device characterized by comprising: a timer for use in the computer;