JPS6441526A - Signal converting circuit - Google Patents

Abstract

PURPOSE:To prevent a through-current of a CMOS circuit by providing a circuit interposed with a load resistor element between two complementary transistors (TRs) having a control input in response to a prescribed input signal between two constant potential points and extracting an output signal from both ends of the said element as a signal conversion circuit. CONSTITUTION:PMOSTs 11, 31, 32 are conductive and NMOSTs 21, 41, 42, 43 are nonconductive when the input signal is at an L level till a time T1 in a circuit where a signal conversion circuit is incorporated as a delay circuit 10 and control signals Y3, Y4 from nodes 51, 52 to an output buffer circuit 9 are kept to H. When the signal A rises at a time T1, the PMOSTs 11, 31, 32 are nonconductive and the NMOSTs 21, 41, 42, 43 are conductive and a time is required when each drain from the NMOST 21 till the NMOST 43 is at a ground level. Thus, the reply delay time of the output signal S1 with respect to the signal A is larger than that of the signal S2 and the trailing time of the signal Y3 is slower than the trailing time T2 of the signal Y4. Since the MOSTs 1, 2 are nonconductive between the times T2 and T3, no through- current IDD flows. This is similar when the signal A descends at a time T5.