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JPS6442837A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6442837A
JPS6442837A JP62200172A JP20017287A JPS6442837A JP S6442837 A JPS6442837 A JP S6442837A JP 62200172 A JP62200172 A JP 62200172A JP 20017287 A JP20017287 A JP 20017287A JP S6442837 A JPS6442837 A JP S6442837A
Authority
JP
Japan
Prior art keywords
circuit
input
cell region
buffer circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62200172A
Other languages
Japanese (ja)
Inventor
Tatsuo Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62200172A priority Critical patent/JPS6442837A/en
Publication of JPS6442837A publication Critical patent/JPS6442837A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To make it possible to freely set a lag time by a method wherein a gate array circuit is composed of an inner cell region and an outer cell region, and the driving circuit of the outer cell region is used as a delay circuit. CONSTITUTION:A two-input AND circuit 10 and non-inverter circuits 11 and 12 are arranged on an inner cell region 1, the input buffer circuit 22 and the outer buffer circuit 31 are connected and they are assigned to the delay circuit 3 inserted between the one input of the two input AND circuit 10 and the non- inverter circuit 11. In ordinary circumstances, the delay time of the output buffer circuit is proportioned to the load capacity. Accordingly, a capacitor 70 and the like is added to the adjusting terminal 60 with which the connected point of the output buffer circuit 31 and the input buffer circuit 22 is led out to outside. As a result, the lag time can be adjusted substantially.
JP62200172A 1987-08-10 1987-08-10 Semiconductor integrated circuit Pending JPS6442837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62200172A JPS6442837A (en) 1987-08-10 1987-08-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62200172A JPS6442837A (en) 1987-08-10 1987-08-10 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6442837A true JPS6442837A (en) 1989-02-15

Family

ID=16419990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62200172A Pending JPS6442837A (en) 1987-08-10 1987-08-10 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6442837A (en)

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