[go: up one dir, main page]

JPS648722A - Buffer circuit using complementary field effect element - Google Patents

Buffer circuit using complementary field effect element

Info

Publication number
JPS648722A
JPS648722A JP62164338A JP16433887A JPS648722A JP S648722 A JPS648722 A JP S648722A JP 62164338 A JP62164338 A JP 62164338A JP 16433887 A JP16433887 A JP 16433887A JP S648722 A JPS648722 A JP S648722A
Authority
JP
Japan
Prior art keywords
inverter
field effect
stage
trs
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164338A
Other languages
Japanese (ja)
Inventor
Takeshi Tokuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62164338A priority Critical patent/JPS648722A/en
Publication of JPS648722A publication Critical patent/JPS648722A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0013Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the through-current without increasing the pattern area by connecting a resistive component in series between field effect components of an inverter of the pre-stage and inputting a voltage across a resistive component to the inverter of the output stage. CONSTITUTION:A resistive element 6 is inserted between P and N-channel transistors(TRs) 5, 7 of an inverter 2 of pre-stage. Moreover, output terminals 8, 9 across the resistor are connected to gates of P and N-channel TRs 10, 11 of an output stage inverter 3 respectively. With a change in the signal from the input terminal 1 given, the capacitance of the gate of the TR 10 or 11 receiving the signal through the resistive component 6 is discharged, delayed only by a specific time constant. Thus, the simultaneous ON-state of the P and N-channel TRs 10, 11 of the inverter 3 of the output stage is evaded.
JP62164338A 1987-06-30 1987-06-30 Buffer circuit using complementary field effect element Pending JPS648722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164338A JPS648722A (en) 1987-06-30 1987-06-30 Buffer circuit using complementary field effect element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164338A JPS648722A (en) 1987-06-30 1987-06-30 Buffer circuit using complementary field effect element

Publications (1)

Publication Number Publication Date
JPS648722A true JPS648722A (en) 1989-01-12

Family

ID=15791274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164338A Pending JPS648722A (en) 1987-06-30 1987-06-30 Buffer circuit using complementary field effect element

Country Status (1)

Country Link
JP (1) JPS648722A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023112506A1 (en) * 2021-12-17 2023-06-22 ソニーセミコンダクタソリューションズ株式会社 Electronic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023112506A1 (en) * 2021-12-17 2023-06-22 ソニーセミコンダクタソリューションズ株式会社 Electronic circuit

Similar Documents

Publication Publication Date Title
JPS6471217A (en) Output buffer circuit
KR880001110A (en) Low noise high output buffer circuit
ATE54391T1 (en) C-MOS INPUT CIRCUIT.
JP2685203B2 (en) Delay circuit
KR900013720A (en) Programmable Logic Circuit
JPS6468021A (en) Logic circuit
DE3685026D1 (en) CLOCKED CMOS SWITCHING WITH AT LEAST ONE CMOS SWITCH.
KR880006850A (en) 3-states complementary MOS integrated circuit
JPS648722A (en) Buffer circuit using complementary field effect element
EP0242523A3 (en) Integrated driving stage for a fet logic circuit
US5982198A (en) Free inverter circuit
JPS5592040A (en) Ttl gate circuit
JPS56162517A (en) Current miller circuit
KR900003725A (en) Input Circuits Performing Test Mode Functions
JPS57192122A (en) Signal generating circuit
JPS6441924A (en) Logic circuit
JPS57178542A (en) Integrated circuit
JPS57197910A (en) Comparator circuit
JPS6412721A (en) Input/output circuit
JPS56166640A (en) Or circuit
KR920011071A (en) Output buffer circuit
JPS6469116A (en) Delay circuit for semiconductor integrated circuit device
JPS57162830A (en) Schmitt trigger circuit
JPS63299518A (en) Binary/ternary converting circuit
JPS57147332A (en) Input circuit