JPS648722A - Buffer circuit using complementary field effect element - Google Patents
Buffer circuit using complementary field effect elementInfo
- Publication number
- JPS648722A JPS648722A JP62164338A JP16433887A JPS648722A JP S648722 A JPS648722 A JP S648722A JP 62164338 A JP62164338 A JP 62164338A JP 16433887 A JP16433887 A JP 16433887A JP S648722 A JPS648722 A JP S648722A
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- field effect
- stage
- trs
- buffer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce the through-current without increasing the pattern area by connecting a resistive component in series between field effect components of an inverter of the pre-stage and inputting a voltage across a resistive component to the inverter of the output stage. CONSTITUTION:A resistive element 6 is inserted between P and N-channel transistors(TRs) 5, 7 of an inverter 2 of pre-stage. Moreover, output terminals 8, 9 across the resistor are connected to gates of P and N-channel TRs 10, 11 of an output stage inverter 3 respectively. With a change in the signal from the input terminal 1 given, the capacitance of the gate of the TR 10 or 11 receiving the signal through the resistive component 6 is discharged, delayed only by a specific time constant. Thus, the simultaneous ON-state of the P and N-channel TRs 10, 11 of the inverter 3 of the output stage is evaded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62164338A JPS648722A (en) | 1987-06-30 | 1987-06-30 | Buffer circuit using complementary field effect element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62164338A JPS648722A (en) | 1987-06-30 | 1987-06-30 | Buffer circuit using complementary field effect element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS648722A true JPS648722A (en) | 1989-01-12 |
Family
ID=15791274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62164338A Pending JPS648722A (en) | 1987-06-30 | 1987-06-30 | Buffer circuit using complementary field effect element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS648722A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023112506A1 (en) * | 2021-12-17 | 2023-06-22 | ソニーセミコンダクタソリューションズ株式会社 | Electronic circuit |
-
1987
- 1987-06-30 JP JP62164338A patent/JPS648722A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023112506A1 (en) * | 2021-12-17 | 2023-06-22 | ソニーセミコンダクタソリューションズ株式会社 | Electronic circuit |
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