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JPS644053A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS644053A
JPS644053A JP15773987A JP15773987A JPS644053A JP S644053 A JPS644053 A JP S644053A JP 15773987 A JP15773987 A JP 15773987A JP 15773987 A JP15773987 A JP 15773987A JP S644053 A JPS644053 A JP S644053A
Authority
JP
Japan
Prior art keywords
leads
chip
semiconductor device
melting
fused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15773987A
Other languages
Japanese (ja)
Inventor
Koji Kaneda
Tetsuji Obara
Minoru Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP15773987A priority Critical patent/JPS644053A/en
Publication of JPS644053A publication Critical patent/JPS644053A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of defect occurrences in a semiconductor device, by providing a fuse function to a route through which leads and/or external terminals of the leads and a semiconductor chip are connected. CONSTITUTION:Fuse function is provided for bonding wires 5 which are used to connect leads 4 and/or external terminals of the leads and a semiconductor chip 3. When an adhesion layer 7 for sealing the chip 3 in a package member 2 is formed of low-melting-point glass (about 450 deg.C in its melting point), the leads 4 and/or the wires 5 are formed of materials with melting points of 500 deg.C or so. Upon the occurrence of excessive current, the leads 4 are fused by transfer heat from the chip 3, and the bonding wires 5 are fused by Joule heat. Consequently, heat generation of the chip 3 is so preventive that a printed wiring substrate 8 can be prevented from fuming. Since only the semiconductor device 1 with occurrence of the excessive current is judged detective, the number of defect occurrences can be reduced in a semiconductor device incorporated in an electronic device.
JP15773987A 1987-06-26 1987-06-26 Semiconductor device Pending JPS644053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15773987A JPS644053A (en) 1987-06-26 1987-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15773987A JPS644053A (en) 1987-06-26 1987-06-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS644053A true JPS644053A (en) 1989-01-09

Family

ID=15656296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15773987A Pending JPS644053A (en) 1987-06-26 1987-06-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS644053A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554432B2 (en) 2005-05-27 2009-06-30 Infineon Technologies Ag Fuse element with trigger assistance
DE102005024347B4 (en) * 2005-05-27 2009-12-17 Infineon Technologies Ag Electrical component with fused power supply connection
DE102005024321B4 (en) * 2005-05-27 2012-03-29 Infineon Technologies Ag protection circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554432B2 (en) 2005-05-27 2009-06-30 Infineon Technologies Ag Fuse element with trigger assistance
DE102005024347B4 (en) * 2005-05-27 2009-12-17 Infineon Technologies Ag Electrical component with fused power supply connection
DE102005024347B8 (en) * 2005-05-27 2010-07-08 Infineon Technologies Ag Electrical component with fused power supply connection
DE102005024321B4 (en) * 2005-05-27 2012-03-29 Infineon Technologies Ag protection circuit
DE102005024321B8 (en) * 2005-05-27 2012-10-04 Infineon Technologies Ag protection circuit

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