JPS6437877A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS6437877A JPS6437877A JP62194672A JP19467287A JPS6437877A JP S6437877 A JPS6437877 A JP S6437877A JP 62194672 A JP62194672 A JP 62194672A JP 19467287 A JP19467287 A JP 19467287A JP S6437877 A JPS6437877 A JP S6437877A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- region
- section
- laminate
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To eliminate the need for a capacitor, and to miniaturize a memory cell while obtaining a memory having large capacitance and high reliability and operating at high speed by making the thickness of a tunnel oxide film thinner than a normal thickness by approximately one figure. CONSTITUTION:n-type source region 2 and drain region 3 are formed to the surface layer section of a p-type Si substrate 1, a section between these regions 2 and 3 is used as a p-type channel region 4, and a gate oxide film 6, a floating gate 7 and a gate electrode 9 for controlling a transistor for switching through an oxide film 8 for insulation acquired by oxidizing the surface of the floating gate 7 are laminated and shaped extending over the central section of the region 3 from the upper section of the region 4. An extremely thin tunnel oxide film 5 in 20-100Angstrom applied to the other half of the region 3 is abutted against the gate oxide film 6, and a bit line 13 is formed at the end section of the oxide film 5 while a source wiring 12 is shaped in the region 2. A section between the wiring 2 and a laminate and a section between the bit line 13 and the laminate are buried with an oxide film 11, and a word line 10 is formed onto the surface of the laminate by employing an opening shaped to the film 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62194672A JPS6437877A (en) | 1987-08-04 | 1987-08-04 | Semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62194672A JPS6437877A (en) | 1987-08-04 | 1987-08-04 | Semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6437877A true JPS6437877A (en) | 1989-02-08 |
Family
ID=16328384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62194672A Pending JPS6437877A (en) | 1987-08-04 | 1987-08-04 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6437877A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5051796A (en) * | 1988-11-10 | 1991-09-24 | Texas Instruments Incorporated | Cross-point contact-free array with a high-density floating-gate structure |
| US5238855A (en) * | 1988-11-10 | 1993-08-24 | Texas Instruments Incorporated | Cross-point contact-free array with a high-density floating-gate structure |
| US5404037A (en) * | 1994-03-17 | 1995-04-04 | National Semiconductor Corporation | EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region |
-
1987
- 1987-08-04 JP JP62194672A patent/JPS6437877A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5051796A (en) * | 1988-11-10 | 1991-09-24 | Texas Instruments Incorporated | Cross-point contact-free array with a high-density floating-gate structure |
| US5238855A (en) * | 1988-11-10 | 1993-08-24 | Texas Instruments Incorporated | Cross-point contact-free array with a high-density floating-gate structure |
| US5404037A (en) * | 1994-03-17 | 1995-04-04 | National Semiconductor Corporation | EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region |
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