JPH0322485A - Field effect transistor for nonvolatile memory - Google Patents
Field effect transistor for nonvolatile memoryInfo
- Publication number
- JPH0322485A JPH0322485A JP15767289A JP15767289A JPH0322485A JP H0322485 A JPH0322485 A JP H0322485A JP 15767289 A JP15767289 A JP 15767289A JP 15767289 A JP15767289 A JP 15767289A JP H0322485 A JPH0322485 A JP H0322485A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- source
- drain
- semiconductor substrate
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は不揮発性メモリ用電界効果トランジスタに関し
、特に浮遊ゲートを有する不揮発性メモリセルに関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor for non-volatile memory, and more particularly to a non-volatile memory cell having a floating gate.
従来の不揮発性メモリ用電界効果トランシスタは、第2
図に示すようにソース12とトレイン13間のチャネル
上に第1のケート酸化膜14、浮遊ゲート電極15、第
2のゲート酸化膜16、制御ゲート電極17を重ね合せ
た(つまり半導体基板の一生面上に14,] 5,16
,1.7が設けられている)構造となっていた。Conventional field effect transistors for non-volatile memory
As shown in the figure, a first gate oxide film 14, a floating gate electrode 15, a second gate oxide film 16, and a control gate electrode 17 are superimposed on the channel between the source 12 and the train 13 (that is, the entire life of the semiconductor substrate is 14, ] 5, 16 on the surface
, 1.7).
上述した従来の不揮発性メモリ用電界効果トランジスタ
は、ソースとドレイン間の平坦なチャネル領域上に第1
のゲーl−酸化膜、浮遊ゲート、第2のゲート酸化膜、
制御ゲートを有する構造となっていたので、集積回路に
おいて制御ケートの上に絶縁膜を形成し、制御ゲートを
乗り越える形でソース又はドレインと接続する電極配線
を形或する場合に、電極配線がソース又はトレイン部で
湾曲する形になり形威しにくいばかりでなく電極配線切
れが発生し易く、半導体記憶装置の歩留り、信頼性上の
障害となるという欠点かある。The conventional field effect transistor for non-volatile memory described above has a first layer on a flat channel region between the source and the drain.
a gate oxide film, a floating gate, a second gate oxide film,
Since the structure has a control gate, when an insulating film is formed on the control gate in an integrated circuit and an electrode wiring is formed to connect to the source or drain by going over the control gate, the electrode wiring is connected to the source or drain. Alternatively, the train portion may be curved, making it difficult to maintain its shape, and the electrode wiring may easily break, which may impede the yield and reliability of the semiconductor memory device.
本発明の不揮発性メモリ用電界効果トランジスタは、半
導体基板の一生面から内部へ向かって掘られた溝の表面
を覆う第1のゲート絶縁膜と、前記第のゲート絶縁膜で
覆われた溝を埋める浮遊ゲート電極と、前記浮遊ゲート
電極上に設けられた第2のゲート絶縁膜と、前記第2の
ゲート絶縁股上に設けられた制御ゲート電極とを有する
というものである。A field effect transistor for a nonvolatile memory according to the present invention includes a first gate insulating film covering the surface of a trench dug inward from the entire surface of a semiconductor substrate, and a trench covered with the first gate insulating film. The device has a floating gate electrode buried therein, a second gate insulating film provided on the floating gate electrode, and a control gate electrode provided on the second gate insulating crotch.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す半導体チップの縦断面
図である。FIG. 1 is a longitudinal sectional view of a semiconductor chip showing an embodiment of the present invention.
p型半導体基板1(シリコン)の表面にソース2とドレ
イン3としてn型不純物拡散層を形戒し、ソース2とト
レイン3間にp型半導体基板1をエッチングして溝を設
けその表面を第1のゲート酸化膜4で被覆し第1の多結
晶シリコン層5を埋め込んで浮遊ゲート電極を形成する
。この後ソース2とドレイン3間の半導体基板表面及び
第1の多結晶シリコン層5上に第2のゲート酸化膜6と
第2の多結晶シリコン層7の制御ゲート電極を形成する
。なお第1のゲート酸化膜4がソース2、ドレイン3と
接しよくするようにしてもよい。An n-type impurity diffusion layer is formed as a source 2 and a drain 3 on the surface of a p-type semiconductor substrate 1 (silicon), and a groove is formed by etching the p-type semiconductor substrate 1 between the source 2 and the drain 3, and the surface is covered with grooves. A first polycrystalline silicon layer 5 is buried to form a floating gate electrode. Thereafter, a second gate oxide film 6 and a control gate electrode of a second polycrystalline silicon layer 7 are formed on the surface of the semiconductor substrate between the source 2 and drain 3 and on the first polycrystalline silicon layer 5. Note that the first gate oxide film 4 may be in good contact with the source 2 and drain 3.
第1のゲート酸化膜4及び第1の多結晶シリコン層の厚
さは、例えはそれぞれ20nm及び60nmにすればよ
い。The thicknesses of the first gate oxide film 4 and the first polycrystalline silicon layer may be, for example, 20 nm and 60 nm, respectively.
浮遊ゲート電極に注入、保持される電荷量によってソー
ス.ドレイン間の抵抗値が変わるのは従来例と同じ原理
によることはいうまでもない。Source depending on the amount of charge injected and held in the floating gate electrode. It goes without saying that the resistance value between the drains changes based on the same principle as in the conventional example.
浮遊ゲート電極が埋め込まれているので、従来例に比較
して平坦性か改善される。Since the floating gate electrode is buried, flatness is improved compared to the conventional example.
以上説明したように本発明は、ソースとドレイン間に半
導体基板の一主面から内部へ向けて掘られた溝に第1の
ゲート酸化膜及び浮遊ゲート電極を埋め込むことにより
、不揮発性メモリ用電界効果トランジスタの制御ゲート
電極を乗り越えてソース又はトレインに接続する電極配
線の形成が容易にでき、半導体集積回路チップの平坦化
が可能であり、半導体集積回路チップの表面に形成する
カバー膜等の欠陥を減少させ、集積回路化に適した不揮
発性メモリ用電界効果トランジスタが得られる効果があ
る。As explained above, the present invention provides an electric field for nonvolatile memory by embedding a first gate oxide film and a floating gate electrode in a trench dug inward from one principal surface of a semiconductor substrate between a source and a drain. It is possible to easily form an electrode wiring that goes over the control gate electrode of an effect transistor and connects to the source or train, and it is possible to flatten the semiconductor integrated circuit chip and eliminate defects in the cover film etc. formed on the surface of the semiconductor integrated circuit chip. This has the effect that a field effect transistor for nonvolatile memory suitable for integration into an integrated circuit can be obtained.
第1図は本発明の一実施例を示す半導体チップの縦断面
図、第2図は従来例を示す半導体チップの縦断面図であ
る。
1,11・・・p型半導体基板、2,12・・・ソース
、3,13・・・ドレイン、4,14・・・第1のゲー
ト酸化膜、5,15・・・第1の多結晶シリコン層(浮
遊ゲート電極)、6.16・・・第2のゲート酸化膜、
7.17・・・第2の多結晶シリコン層(制御ゲート電
極)。FIG. 1 is a vertical sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a vertical sectional view of a semiconductor chip showing a conventional example. 1, 11... p-type semiconductor substrate, 2, 12... source, 3, 13... drain, 4, 14... first gate oxide film, 5, 15... first multilayer Crystalline silicon layer (floating gate electrode), 6.16... second gate oxide film,
7.17...Second polycrystalline silicon layer (control gate electrode).
Claims (1)
面を覆う第1のゲート絶縁膜と、前記第のゲート絶縁膜
で覆われた溝を埋める浮遊ゲート電極と、前記浮遊ゲー
ト電極上に設けられた第2のゲート絶縁膜と、前記第2
のゲート絶縁膜上に設けられた制御ゲート電極とを有す
ることを特徴とする不揮発性メモリ用電界効果トランジ
スタ。a first gate insulating film covering the surface of a trench dug inward from one main surface of the semiconductor substrate; a floating gate electrode filling the trench covered with the first gate insulating film; and a floating gate electrode on the floating gate electrode. a second gate insulating film provided on the second gate insulating film;
A field effect transistor for a nonvolatile memory, comprising a control gate electrode provided on a gate insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15767289A JPH0322485A (en) | 1989-06-19 | 1989-06-19 | Field effect transistor for nonvolatile memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15767289A JPH0322485A (en) | 1989-06-19 | 1989-06-19 | Field effect transistor for nonvolatile memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0322485A true JPH0322485A (en) | 1991-01-30 |
Family
ID=15654859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15767289A Pending JPH0322485A (en) | 1989-06-19 | 1989-06-19 | Field effect transistor for nonvolatile memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0322485A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2807208A1 (en) * | 2000-03-29 | 2001-10-05 | St Microelectronics Sa | Non-volatile memory semiconductor device has floating gate extending between the source and drain regions, and control gate situated above floating gate |
DE10054172A1 (en) * | 2000-11-02 | 2002-05-16 | Infineon Technologies Ag | Semiconductor memory cell and method for its production |
JP2006066916A (en) * | 2004-08-27 | 2006-03-09 | Samsung Electronics Co Ltd | SONOS memory cell and method of forming the same |
-
1989
- 1989-06-19 JP JP15767289A patent/JPH0322485A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2807208A1 (en) * | 2000-03-29 | 2001-10-05 | St Microelectronics Sa | Non-volatile memory semiconductor device has floating gate extending between the source and drain regions, and control gate situated above floating gate |
US6642108B2 (en) | 2000-03-29 | 2003-11-04 | Stmicroelectronics Sa | Fabrication processes for semiconductor non-volatile memory device |
DE10054172A1 (en) * | 2000-11-02 | 2002-05-16 | Infineon Technologies Ag | Semiconductor memory cell and method for its production |
DE10054172C2 (en) * | 2000-11-02 | 2002-12-05 | Infineon Technologies Ag | Semiconductor memory cell with a floating gate electrode arranged in a trench and method for the production thereof |
US6940121B2 (en) | 2000-11-02 | 2005-09-06 | Infineon Technology Ag | Semiconductor memory cell |
JP2006066916A (en) * | 2004-08-27 | 2006-03-09 | Samsung Electronics Co Ltd | SONOS memory cell and method of forming the same |
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