JP4940533B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor integrated circuit device .

2. Description of the Related Art In recent years, with the increase in integration due to miniaturization of elements, the number of gates used for transistors has greatly increased, and the layout of wiring layers that connect between logic circuit cells and between micro functional blocks has become complicated.
The wiring layer is desirably connected between the cells or the blocks at a shortest distance or an equal distance, but it is difficult to connect the wiring layers in this way due to the layout.
In order to solve such problems, a method of forming a wiring layer not only on the front surface side of the substrate but also on the back surface side of the substrate is known (see Patent Document 1).

Here, a semiconductor integrated circuit device having such a configuration will be described with reference to FIG.
The semiconductor integrated circuit device 70 includes a gate electrode 54 formed at a predetermined position on a single crystal silicon layer 71 separated by an element isolation region 52 via a gate insulating film 53, and both sides of the gate electrode 54. A transistor 57 composed of an active layer (a source region 55 and a drain region 56) formed in the single crystal silicon layer 71 is formed, and is connected to the transistor 57 on the front surface side and the back surface side of the single crystal silicon layer 71. Each wiring layer is formed.
A sidewall insulating film 72 is formed on the sidewall of the gate electrode 54, and LDD regions (55A, 56A) are formed inside the source region 55 and the drain region 56. 73 is a silicide layer, and 76 is an etching stopper film.

  In this semiconductor integrated circuit device 70, since the active layer (source region 55, drain region 56) of the transistor 57 is shallower than the thickness D of the single crystal silicon layer 71, the distance between the source region 55 and the drain region 56 is reduced. A depletion layer 68 is partially formed in the body region 711 below the channel region. The wiring formed on the back side is connected to the transistor 57 by the connection layer 64.

The wiring layer on the surface side includes a first wiring 74 connected and formed via a contact wiring 61 in the interlayer insulating film 60 formed on the surface side of the single crystal silicon layer 71, and the first layer. The second layer wiring 75 is formed again on the wiring 74 through the contact wiring 61.
A planarizing film 77 made of a passivation film is formed on the uppermost wiring 75, and a support substrate 79 is attached on the planarizing film 77 via an adhesive layer 78.

The wiring layer formed on the back surface side is connected to the back surface side of the single crystal silicon layer 71 via the contact wiring 61 in the interlayer insulating film 60 formed via the buried oxide film (so-called BOX layer) 80. The wiring 81 is formed.
JP-A-9-260669

Incidentally, when the semiconductor integrated circuit device 70 having the configuration shown in FIG. 13 is manufactured, the following problems may occur.
That is, in the case of the semiconductor integrated circuit device 70, the wiring 81 formed on the back surface side is connected to the transistor 57 (drain region 56) formed on the front surface side by the connection layer 64.
However, in this connection layer 64, after forming the transistor 57 and the wiring (74, 75) on the front surface side of the single crystal silicon layer 71, a contact hole 611 is formed at a position corresponding to the drain region 56 from the back surface side. Since ion implantation is performed in the single crystal silicon layer 71 through the contact hole 611 and then the ion implanted region is activated, for example, it is formed first by high-temperature heat treatment at the time of activation. There is a risk that the wiring (74, 75) made of a material having low heat resistance may be thermally affected.

  Further, when the contact hole 611 is formed so as to be displaced from the position corresponding to the drain region 56 due to, for example, a displacement of the mask, the connection layer 64 is not connected to the drain region 56 or between the drain region 56. A sufficient connection area cannot be obtained. When such a connection failure occurs, for example, an operation failure of the device itself is caused.

  As shown in FIG. 13, such a problem occurs not only in the case of manufacturing a semiconductor integrated circuit device having wiring on the front surface side and the back surface side based on the SOI substrate, but also on the front surface side and the back surface side based on the simple substrate. It may also occur when a semiconductor integrated circuit device having a wiring is manufactured.

In view of the above, the present invention provides a method for manufacturing a semiconductor integrated circuit device that can form a connection layer without affecting the wiring layer on the front surface side and without causing a connection failure.

The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a connection layer extending from the front surface side to the back surface side in a semiconductor layer, and forming a transistor on the front surface side of the semiconductor layer on which the connection layer is formed And a step of directly connecting the connection layer and the drain region of the transistor, and a step of forming a first wiring layer by connecting to the source region of the transistor on the surface side of the semiconductor layer where the transistor is formed. Thereafter, a step of connecting to the connection layer and forming a second wiring layer on the back surface side of the semiconductor layer is provided.

According to the method for manufacturing a semiconductor integrated circuit device of the present invention described above, a step of forming a connection layer reaching from the front surface side to the back surface side in the semiconductor layer, and on the surface side of the semiconductor layer in which the connection layer is formed , Forming a transistor, directly connecting the connection layer and the drain region of the transistor, and forming a first wiring layer on the surface side of the semiconductor layer in which the transistor is formed , connected to the source region of the transistor And a step of forming a second wiring layer by connecting to the connection layer on the back surface side of the semiconductor layer and then forming the transistor and the first wiring layer on the surface side of the semiconductor layer, for example. After the formation, the thermal influence on the first wiring layer can be suppressed as compared with a method of forming a connection layer for connecting the drain region of the transistor and the second wiring layer in the semiconductor layer. .
In addition, since the connection layer is formed first, it is possible to reduce the occurrence of connection failure between the connection layer and the drain region of the transistor. Further, for example, since it is not necessary to consider misalignment with the drain region of the transistor, the connection layer can be easily formed.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a connection layer reaching from the front surface side to the back surface side is formed on the semiconductor layer on the substrate in which the semiconductor layer is laminated on the support substrate via the insulating film. Forming a transistor on the surface side of the semiconductor layer on which the connection layer is formed and directly connecting the connection layer and the drain region of the transistor; and on the surface side of the semiconductor layer on which the transistor is formed , connected to the source region of the transistor, forming a first wiring layer, then removing the support substrate, the back surface side of the semiconductor layer after the supporting substrate is removed, connected to a connection layer And a step of forming a second wiring layer.

According to the manufacturing method of the semiconductor integrated circuit device of the present invention described above, the connection layer reaching the semiconductor layer from the front surface side to the back surface side with respect to the substrate in which the semiconductor layer is laminated on the support substrate via the insulating film. Forming a transistor on the surface side of the semiconductor layer where the connection layer is formed , directly connecting the connection layer and the drain region of the transistor, and forming the transistor in the semiconductor layer where the transistor is formed Connecting to the source region of the transistor on the front surface side, forming a first wiring layer, then removing the support substrate , and connecting to the back surface side of the semiconductor layer after the support substrate is removed Forming the second wiring layer in connection with the layer, for example, after forming the transistor and the first wiring layer on the surface side of the semiconductor layer, the drain region of the transistor and the first wiring layer are formed on the semiconductor layer. Compared to a method of forming a connection layer for connecting of the wiring layer, it is possible to suppress the thermal effect on the first wiring layer.
In addition, since the connection layer is formed first, it is possible to reduce the occurrence of connection failure between the connection layer and the drain region of the transistor. Further, for example, since it is not necessary to consider misalignment with the drain region of the transistor, the connection layer can be easily formed.

The method for manufacturing a semiconductor integrated circuit device according to the present invention is such that only a back surface side of a semiconductor layer is formed by ion implantation from the front surface side of the semiconductor layer with respect to a substrate on which a semiconductor layer is formed on a support substrate via an insulating film. A step of forming an impurity region for fixing the potential of the semiconductor layer, a step of forming a transistor on the surface side of the semiconductor layer in which the impurity region is formed , and a source of the transistor on the surface side of the semiconductor layer. A step of forming a first wiring layer connected to the region, a step of removing the support substrate, and a step of forming a second wiring layer connected to the impurity region on the back surface side of the semiconductor layer. To have.

According to the manufacturing method of the semiconductor integrated circuit device of the present invention described above, the semiconductor layer is formed by ion implantation from the surface side of the semiconductor layer with respect to the substrate on which the semiconductor layer is formed on the support substrate via the insulating film. A step of forming an impurity region for fixing the potential of the semiconductor layer only on the back surface side, a step of forming a transistor on the surface side of the semiconductor layer where the impurity region is formed, and a surface side of the semiconductor layer, A step of forming a first wiring layer connected to the source region of the transistor, a step of removing the support substrate, and a second wiring layer connected to the impurity region on the back side of the semiconductor layer For example, after forming the transistor and the first wiring layer on the front surface side of the semiconductor layer, an impurity region for fixing the potential of the non-depleted region of the transistor is formed in the semiconductor layer from the back surface side. Compared with the method so as to, it is possible to suppress the thermal effect, for example, in the first wiring layer.
In addition, it is possible to manufacture a semiconductor integrated circuit device having a configuration in which an increase in drain current due to a change in threshold value of the first transistor is suppressed.

According to the method for manufacturing a semiconductor integrated circuit device of the present invention, after the connection layer reaching from the front surface side to the back surface side is formed on the semiconductor layer, and the transistor and the first wiring layer are formed on the front surface side of the semiconductor layer. Since the second wiring layer is formed on the back surface side of the semiconductor layer, the connection layer is formed without affecting the wiring layer on the front surface side and without causing poor connection with the transistor on the front surface side. be able to.

Further, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, only the back surface side of the semiconductor layer is implanted by ion implantation from the front surface side with respect to the substrate in which the semiconductor layer is laminated on the support substrate via the insulating film. After forming the impurity region, the first transistor and the first wiring layer are formed on the front surface side of the semiconductor layer, and the second wiring layer is formed on the back surface side of the semiconductor layer so as to be connected to the impurity region. It is possible to manufacture a semiconductor integrated circuit device having a configuration in which an increase in drain current due to a change in threshold voltage of a transistor is suppressed without affecting the wiring layer on the surface side.
Therefore, it is possible to obtain a semiconductor integrated circuit device having a configuration in which reliability is ensured and a substrate floating effect such as a kink phenomenon is suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 5 shows a schematic configuration diagram of an embodiment of a semiconductor integrated circuit device to which the method for manufacturing a semiconductor integrated circuit device according to the present invention is applied.
The semiconductor integrated circuit device 1 includes a gate electrode 14 formed at a predetermined position on a single crystal silicon layer (semiconductor layer) 4 separated by an element isolation region 6 via a gate insulating film 13, and the gate electrode A MOS type field effect transistor (hereinafter referred to as MOSFET) 12 composed of an active layer (source region 15 and drain region 16) formed in the single crystal silicon layer 4 is formed on both sides of the single crystal silicon layer 14. A wiring layer (first wiring layer) connected to one active layer (source region 15) of MOSFET 12 is formed on the surface side of silicon layer 4, and the other side of MOSFET 12 is formed on the back surface side of single crystal silicon layer 4. A wiring layer (second wiring layer) connected to the active layer (drain region 16) is formed.
A side wall insulating film 17 is formed on the side wall of the gate electrode 14, and LDD regions (15 A, 16 A) are formed inside the source region 15 and the drain region 16. In some cases, a region called a halo or a pocket is formed below the region. Further, a silicide layer 18 is formed on the surface side of the source region 15 and the drain region 16 and on the gate electrode 14, and an etching stopper film 19 is formed on the entire surface of the single crystal silicon layer 4. In the case shown in FIG. 5, the structure in which the silicide layer 18 is formed is shown, but the silicide layer 18 can be removed if necessary.

The wiring layer on the surface side is a first-layer wiring 211 connected and formed at a position corresponding to the source region 15 via a contact wiring 24 in the interlayer insulating film 23 formed on the single crystal silicon layer 4. And a second-layer wiring 212 formed on the first-layer wiring 211 via the contact wiring 24 again.
A planarizing film 25 made of a passivation film is formed on the uppermost wiring 212, and a support substrate 27 is attached on the planarizing film 25 with an adhesive layer 26 interposed therebetween.

  The wiring layer formed on the back surface side is the drain of the MOSFET 12 formed on the front surface side in the interlayer insulating film 23 formed on the back surface side of the single crystal silicon layer 4 via the buried oxide film (so-called BOX layer) 3. A contact wiring 24 formed at a position corresponding to the region 16 and a first-layer wiring 221 connected to the contact wiring 24 are formed.

  Here, in the case of the semiconductor integrated circuit device 1 of the present embodiment, since the film thickness D of the single crystal silicon layer 4 is formed thick (several tens to 100 nm), it is formed in the single crystal silicon layer 4. The body region 41 below the channel region is not completely depleted, and a depletion layer 28 is partially formed. Therefore, by forming the connection layer 8 at a position corresponding to the drain region 16 in the single crystal silicon layer 4, the MOSFET 12 formed on the front surface side and the wiring 221 on the back surface side are connected.

In the present embodiment, in particular, the wiring 221 formed on the back surface side is formed on the front surface side via the connection layer 8 formed from the front surface side to the back surface side in the single crystal silicon layer 4. In other words, in the case of the present embodiment, the connection layer 8 is in direct contact with the inside of the drain region 16 so that the MOSFET 12 and the wiring 221 on the back surface side are connected.
In addition to this, for example, only one side of the connection layer 8 may be in direct contact with the inside of the drain region 16 so that the MOSFET 12 and the wiring 221 on the back surface side are connected.

According to the semiconductor integrated circuit device 1 of the present embodiment described above, the connection layer 8 that connects the MOSFET 12 formed on the front surface side and the wiring 221 formed on the back surface passes through the drain region 16 of the MOSFET 12. Therefore, a reliable connection can be obtained between the connection layer 8 and the drain region 16. In addition, a sufficient connection area can be obtained between the connection layer 8 and the drain region 16.
As a result, a semiconductor integrated circuit device in which poor connection between the MOSFET 12 on the front surface side and the wiring 221 on the back surface side is suppressed can be obtained.

Next, as an embodiment of the manufacturing method of the present invention, a method for manufacturing the semiconductor integrated circuit device 1 having the configuration shown in FIG. 5 will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the part corresponding to FIG.
First, as shown in FIG. 1A, an SOI substrate 5 in which a single crystal silicon layer (so-called SOI layer) 4 is formed on a support substrate 2 made of, for example, silicon via a buried oxide film (so-called BOX layer) 3 is formed. prepare.

  As the SOI substrate 5, for example, a substrate formed by using a bonding method or a hydrogen ion implantation method can be used. In particular, for example, the SOI substrate 5 in which the single crystal silicon layer 4 is formed on the support substrate 2 through the buried oxide film 3 formed by thermally oxidizing the single crystal silicon layer formed by epitaxial growth is as follows: It is desirable that the interface between the buried oxide film 3 and the single crystal silicon layer 4 has few defects. The film thickness of the buried oxide film 3 and the single crystal silicon layer 4 can be set arbitrarily.

  Next, an element isolation region 6 is formed at a predetermined position of the single crystal silicon layer 4 of the SOI substrate 5 by using, for example, an STI (shallow trench element isolation) method, and as shown in FIG. 1B, the single crystal silicon layer 4 Inside, element formation regions 7 separated by element isolation regions 6 are formed.

  In this embodiment, in particular, before the transistors and wiring layers are formed on the front surface side of the SOI substrate 5, the connection layer 8 that connects the transistors formed on the front surface side and the wiring layers on the back surface side is formed. To do.

  That is, by forming the connection layer 8 before the transistors and wiring layers are formed on the surface side of the SOI substrate 5 in this way, after the transistors and wiring layers are formed on the surface side of the substrate as in the prior art, Compared with the case where the connection layer is formed, it is possible to prevent a thermal influence on the wiring layer made of a material having low heat resistance formed on the surface side of the substrate.

The connection layer 8 can be formed as follows, for example.
First, by etching the single crystal silicon layer 4, so-called holes 9 such as trench grooves and via holes are formed at predetermined positions in the element formation region 7. Here, the etching of the single crystal silicon layer 4 is performed until reaching the buried oxide film (BOX layer) 3.
At this time, since a high selection ratio can be ensured between the single crystal silicon layer 4 and the buried oxide film 3, the holes 9 having a uniform depth are formed in the single crystal silicon without affecting the buried oxide film 3. The interface can be formed up to the interface between the layer 4 and the buried oxide film 3. In addition, since the oxide film 3 serves as a stopper, the hole 9 having a uniform depth is formed in the single crystal silicon layer 4 and the buried oxide film without affecting the buried oxide film 3 and the support substrate 2 in this respect. 3 can be formed.
Then, polycrystalline silicon 10 doped with impurities is deposited in the hole 9 by CVD. Thereafter, the polycrystalline silicon 10 other than the inside of the hole 9 is removed by polishing using, for example, an EB method or a CMP method. Thereby, the connection layer 8 as described above is formed.
The impurity doped into the polycrystalline silicon 10 has the same conductivity type (for example, N type) as the source region and the drain region of a transistor formed in a process described later.

Next, according to a conventionally known method, as shown in FIG. 2C, a MOS type field effect transistor (hereinafter referred to as MOSFET) 12 is formed on the surface side of the SOI substrate 5.
Specifically, first, a gate electrode 14 is formed at a predetermined position on the element formation region 7 via a gate oxide film 13, and further, an LDD region (15 A, 16 A is formed at a predetermined position in the element formation region 7. ). In some cases, a region called a halo or a pocket is formed below the region.
Next, a sidewall insulating film 17 is formed on the sidewall of the gate electrode 14, and impurities (for example, N-type) are ion-implanted into the element formation region 7 using the gate electrode 14 with the sidewall insulating film 17 formed as a mask. The source region 15 and the drain region 16 are formed at predetermined positions in the element formation region 7 by activating the region into which the impurity is implanted.
Thereafter, a silicide layer 18 is formed on the surface side of the source region 15 and the drain region 16 and on the gate electrode 14, and an etching stopper film 19 is formed on the entire surface including the MOSFET 12.

  Here, since the connection layer 8 is formed at the position where the drain region is formed when performing ion implantation, the ion implantation region is formed so as to straddle the connection layer 8. Therefore, after the activation, the connection layer 8 is formed through the drain region 16.

Next, as shown in FIG. 2D, a wiring layer on the surface side is formed on the SOI substrate 5.
Specifically, first, for example, after an interlayer insulating film 23 is formed on the entire surface of the SOI substrate 5 and planarized, a contact region is formed at a position corresponding to the drain region 16 of the planarized interlayer insulating film 23. The wiring 24 is formed. Then, a first layer wiring 211 is formed so as to be connected to the contact wiring 24.
Next, after the interlayer insulating film 23 is formed again on the entire surface including the first layer wiring 211 and planarized, a position corresponding to the first layer wiring 211 of the planarized interlayer insulating film 23 is obtained. After forming the contact wiring 24 again, a second-layer wiring 212 is formed so as to be connected to the contact wiring 24.
In the case shown in FIG. 2C, the case where the wiring layer has a two-layer structure is shown. However, when there are three or more layers, such a process is repeated.
Thereafter, a planarizing film 25 made of a passivated film made of, for example, a SiN film or a SiON film is formed on the outermost wiring 212.

Next, an adhesive layer 26 is applied on the planarizing film 25 in order to bond the support substrate in a process described later. Here, as the adhesive layer 26, it is desirable to use a material having as high a heat resistance as possible. For example, a coating system such as an SOG film or an organic film, or an adhesive sheet can be used. Next, the support substrate 27 is pasted, so that the support substrate 27 is pasted on the wiring layer as shown in FIG. 3E.
Note that the reason why the support substrate 27 is attached to the surface side of the SOI substrate 5 is to ensure mechanical strength when the support substrate 2 is polished to reduce the thickness of the SOI substrate 5 in a process described later. is there.

  Next, by turning upside down, as shown in FIG. 3F, the back side of the SOI substrate 5, that is, the support substrate 2 is exposed.

Next, the support substrate 2 is removed, and the buried oxide film 3 of the SOI substrate 5 is exposed as shown in FIG. 4G.
At this time, the support substrate 2 is first polished using mechanical polishing or CMP, and when the surface approaches the vicinity of the buried oxide film 3, for example, the support substrate 2 and the buried oxide film 3 are switched to the wet etching method. The support substrate 2 is etched under the condition that the etching rate can be secured.
By switching between polishing and etching stepwise in this way, the surface of the buried oxide film 3 can be completely exposed without affecting the buried oxide film 3.

Next, as shown in FIG. 4H, a wiring layer on the back surface side is formed on the buried oxide film 3.
Specifically, first, after an interlayer insulating film 23 is formed on the entire surface of the buried oxide film 3 and planarized, contact wiring 24 is formed at a position corresponding to the connection layer 8 of the interlayer insulating film 23. A connection 221 is formed so as to connect to the contact wiring 24 on the planarized interlayer insulating film 23.
At this time, as described above, since the connection layer 8 is formed up to the interface between the single crystal silicon layer 4 and the buried oxide film 3, for example, the contact wiring 24 can be reliably connected to the connection layer 8. it can.
Similar to the case of the wiring layer on the surface side described above, such a process is repeated when there are three or more wiring layers, for example.

  Thereafter, the semiconductor integrated circuit device 1 having the structure in which the wiring layers are formed on the front surface side and the back surface side as shown in FIG.

  According to the manufacturing method of the semiconductor integrated circuit device 1 of the present embodiment described above, the single crystal silicon layer is formed from the surface side before the MOSFET 12 and the wirings (211, 212) are formed on the surface side of the single crystal silicon layer 4. 4, the connection layer 8 is formed first, so that, for example, after the MOSFET 12 and the wirings (211, 212) are formed on the front surface side of the single crystal silicon layer 4, Compared with a method in which a contact hole is formed at a position corresponding to the drain region 16, ion implantation is performed in the single crystal silicon layer 4 through the contact hole, and then the connection region 8 is formed by activating the ion implanted region. Suppresses the thermal effect on the wiring (211 and 212) made of a material having low heat resistance formed on the surface side of the single crystal silicon layer 4 Rukoto can.

Further, as compared with a conventional method in which a contact hole is formed and ions are implanted into the substrate from the contact hole to form a connection layer, the connection layer 8 is formed on the SOI substrate 5 first, so that the mask is formed. Connection failures between the connection layer 8 and the drain region 16 due to misalignment or the like can be reduced.
In addition, since it is not necessary to consider the displacement of the mask or the like, the connection layer 8 can be easily formed.

In the present embodiment, in the step shown in FIG. 1B, a hole 9 is formed at a predetermined position of the single crystal silicon layer 4, and polycrystalline silicon doped with impurities using the CVD method is formed in the hole 9. The connection layer 8 is formed by deposition. In this step, as shown in FIG. 6, for example, the connection layer 81 is formed by ion-implanting impurities into a predetermined position of the single crystal silicon layer 4 from the surface side. Can also be formed. Subsequent steps are the same as the steps shown in FIGS. 2C to 4H, whereby the semiconductor integrated circuit device 111 has a configuration in which wiring layers are formed on the front side and the back side, respectively, as shown in FIG. Can be obtained.
The impurity implantation conditions can be arbitrarily set.

  The ion implantation region to be the connection layer 8 can be activated following the ion implantation, but at the same time as the activation of the source region 15 and the drain region 16 of the MOSFET 12 formed in the subsequent process. It can also be done.

  In the above-described embodiment, the present invention is based on the SOI substrate 5 in which the semiconductor layer (single crystal silicon layer) 4 is laminated on the support substrate 2 via the buried oxide film (insulating film) 3. Although the description has been made by applying to the case of manufacturing a semiconductor integrated circuit device having wiring layers on the side and the back side, a semiconductor having wiring layers on the front side and the back side based not on the SOI substrate 5 but on a simple substrate. The present invention can also be applied when manufacturing an integrated circuit device.

Even in such a case, as in the case of the present embodiment, it is possible to suppress the thermal influence on the wiring made of a material having low heat resistance formed on the surface side of the substrate.
In addition, since the connection layer is formed on the substrate first, connection failure between the connection layer and the drain region due to misalignment of the mask or the like can be reduced. In addition, since it is not necessary to consider the positional deviation of the mask, the connection layer can be easily formed.

Next, in describing another embodiment of a semiconductor integrated circuit device according to the present invention, first,
One mode of a semiconductor integrated circuit device to which a method for manufacturing a semiconductor integrated circuit device according to the present invention is applied will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the part corresponding to FIG.
The semiconductor integrated circuit device 11 includes a gate electrode 14 formed at a predetermined position on a single crystal silicon layer 4 separated by an element isolation region 6 via a gate insulating film 13, and both sides of the gate electrode 14. A MOS field effect transistor (hereinafter referred to as a MOSFET) 12 composed of an active layer (source region 15 and drain region 16) formed in the single crystal silicon layer 4 is formed and connected to the MOSFET 12. The wiring layers are formed on the front surface side and the back surface side of the single crystal silicon layer 4, respectively. A side wall insulating film 17 is formed on the side wall of the gate electrode 14, and LDD regions (15 A, 16 A) are formed inside the source region 15 and the drain region 16. In some cases, a region called a halo or a pocket is formed below the region. A silicide layer 18 is formed on the surface side of the source region 15 and the drain region 16 and on the gate electrode 14, and an etching stopper film 19 is formed on the entire surface including the MOSFET 12.

The wiring layer on the surface side is a first-layer wiring 211 connected and formed at a position corresponding to the source region 15 via a contact wiring 24 in the interlayer insulating film 23 formed on the single crystal silicon layer 4. And a second-layer wiring 212 formed on the first-layer wiring 211 via the contact wiring 24 again.
Note that a planarizing film 25 made of a passivation film is formed on the uppermost wiring 212, and a support substrate 27 is attached to the planarizing film 25 with an adhesive layer 26 interposed therebetween.

  The wiring layer on the back surface side was formed on the back surface side of the single crystal silicon layer 4 in an interlayer insulating film 23 formed via a buried oxide film (so-called BOX layer) 3 corresponding to a contact layer described later. A contact wiring 24 and a first-layer wiring 221 connected to the contact wiring 24 are formed.

In the semiconductor integrated circuit device 11 having such a configuration, an impurity region (contact layer) 30 for fixing the potential of the body region 41 of the MOSFET 12 formed on the front surface side is formed on the back surface side of the single crystal silicon layer 4. Has been.
Specifically, the contact layer 30 is formed at a predetermined position on the interface between the single crystal silicon layer 4 and the buried oxide film (so-called BOX layer) 3 on the back side of the element formation region 7 where the MOSFET 12 is formed. . And this contact layer 30 is connected with the wiring 221 formed in the back surface side.
The formation position of the contact layer 30 is not limited to a position immediately below the gate electrode 14 and is not particularly limited as long as it is within the element formation region 7.

  That is, by forming the contact layer 30 for fixing the potential of the body region 41 of the MOSFET 12 and changing the voltage applied to the contact layer 30 through the wiring 221 on the back surface side, the potential of the body region 41 is fixed. Can do. As a result, holes accumulated in the body region 41 can be extracted, so that the problem that the amount of accumulated holes in the body region 41 increases can be solved.

  In this case, for example, the potential of the body region 41 can be suppressed from rising to the plus (+) side, and an increase in drain current due to fluctuations in the threshold voltage (Vth) of the MOSFET 12 can be suppressed. It is possible to prevent an increase (kink) in drain current.

  Further, in this semiconductor integrated circuit device 11, the contact layer 30 for fixing the potential of the body region 41 is formed on the back side, not on the front side where the layout is complicated. The layout on the surface side can be simplified compared to the configuration in which the contact layer 30 for fixing the potential is formed.

Next, as another embodiment of the present invention, an embodiment of a method for manufacturing the semiconductor integrated circuit device 11 having the configuration shown in FIG. 12 will be described with reference to FIGS. Note that portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and redundant description is omitted.
First, as shown in FIG. 8A, an SOI substrate 5 in which a single crystal silicon layer (so-called SOI layer) 4 is formed on a support substrate 2 made of, for example, silicon via a buried oxide film (so-called BOX layer) 3 is formed. prepare.

As the SOI substrate 5, for example, a substrate formed by using a bonding method or a hydrogen ion implantation method can be used. In particular, for example, the SOI substrate 5 in which the single crystal silicon layer 4 is formed on the support substrate 2 through the buried oxide film 3 formed by thermally oxidizing the single crystal silicon layer formed by epitaxial growth is buried oxide. It is desirable that the interface between the film 3 and the single crystal silicon layer 4 has few defects.
The film thickness of the buried oxide film 3 and the single crystal silicon layer 4 can be set arbitrarily.

  Next, an element isolation region 6 is formed at a predetermined position of the single crystal silicon layer 4 of the SOI substrate 5 by using, for example, an STI (shallow trench element isolation) method, and as shown in FIG. 8B, the single crystal silicon layer 4 Inside, element formation regions 7 separated by element isolation regions 6 are formed.

In this embodiment, in particular, before forming the transistor and the wiring layer on the surface side of the SOI substrate 5, the contact layer 30 for fixing the potential of the body region 41 of the transistor is formed before the surface side. End up.
Specifically, an impurity is implanted into a predetermined position in the single crystal silicon layer 4 separated by the element isolation region 6 by ion implantation, and then the implanted region is activated to reduce the resistance. The contact layer 30 is formed.
Note that it is desirable that the implanted impurities have the same conductivity type (for example, N type) as the single crystal silicon layer 4.

  That is, in this way, by forming the contact layer 30 before the transistors and wiring layers are formed on the surface side of the SOI substrate 5, for example, from a material having low heat resistance formed on the surface side of the substrate. It is possible to prevent thermal influence on the wiring (211 and 212).

Next, in accordance with a conventionally known method, as shown in FIG. 8C, a MOS type field effect transistor (hereinafter referred to as MOSFET) 12 is formed on the surface side of the SOI substrate 5.
Specifically, first, a gate electrode 14 is formed at a predetermined position on the element formation region 7 via a gate oxide film 13, and further, an LDD region (15 A, 16 A is formed at a predetermined position in the element formation region 7. ). In some cases, a region called a halo or a pocket is formed below the region.
Next, a sidewall insulating film 17 is formed on the sidewall of the gate electrode 14, and impurities (for example, N-type) are ion-implanted into the element formation region 7 using the gate electrode 14 with the sidewall insulating film 17 formed as a mask. The source region 15 and the drain region 16 are formed at predetermined positions in the element formation region 7 by activating the region into which the impurity is implanted.
Thereafter, a silicide layer 18 is formed on the surface side of the source region 15 and the drain region 16 and on the gate electrode 14, and an etching stopper film 19 is formed on the entire surface including the MOSFET 12.

Next, as shown in FIG. 9D, a wiring layer on the surface side is formed on the SOI substrate 5.
Specifically, first, for example, after an interlayer insulating film 23 is formed on the entire surface of the SOI substrate 5 and planarized, a contact region is formed at a position corresponding to the drain region 16 of the planarized interlayer insulating film 23. The wiring 24 is formed. Then, a first layer wiring 211 is formed so as to be connected to the contact wiring 24.
Next, after the interlayer insulating film 23 is formed again on the entire surface including the first layer wiring 211 and planarized, a position corresponding to the first layer wiring 211 of the planarized interlayer insulating film 23 is obtained. After forming the contact wiring 24 again, a second-layer wiring 212 is formed so as to be connected to the contact wiring 24.
In the case shown in FIG. 9D, the case where the wiring layer has a two-layer structure is shown. However, in the case of three or more layers, such a process is repeated.
Thereafter, a planarizing film 25 made of a passivated film made of, for example, a SiN film or a SiON film is formed on the outermost wiring 212.

Next, an adhesive layer 26 is applied on the planarizing film 25 in order to bond the support substrate in a process described later. Here, as the adhesive layer 26, it is desirable to use a material having as high a heat resistance as possible. For example, a coating system such as an SOG film or an organic film, or an adhesive sheet can be used. Next, the support substrate 27 is pasted, so that the support substrate 27 is pasted onto the wiring layer as shown in FIG. 9E.
Note that the reason why the support substrate 27 is attached to the surface side of the SOI substrate 5 is to ensure mechanical strength when the support substrate 2 is polished to reduce the thickness of the SOI substrate 5 in a process described later. is there.

  Next, by turning upside down, as shown in FIG. 10F, the back side of the SOI substrate 5, that is, the support substrate 2 is exposed.

Next, the exposed support substrate 2 is polished so that the buried oxide film 3 of the SOI substrate 5 is exposed as shown in FIG. 10G.
At this time, the support substrate 2 is first polished using mechanical polishing or CMP, and when the surface approaches the vicinity of the buried oxide film 3, for example, the support substrate 2 and the buried oxide film 3 are switched to the wet etching method. The support substrate 2 is etched under the condition that the etching rate can be secured.
By switching between polishing and etching stepwise in this way, the surface of the buried oxide film 3 can be completely exposed without affecting the buried oxide film 3.

Next, as shown in FIG. 11, a wiring layer on the back surface side is formed on the buried oxide film 3.
Specifically, first, after an interlayer insulating film 23 is formed on the entire surface of the buried oxide film 3 and planarized, contact wiring 24 is formed at a position corresponding to the connection layer 8 of the interlayer insulating film 23. A connection 221 is formed so as to connect to the contact wiring 24 on the planarized interlayer insulating film 23.
At this time, since the connection layer 8 is formed up to the interface between the single crystal silicon layer 4 and the buried oxide film 3, the contact wiring 24 can be reliably connected to the connection layer 8 as described above.
Similar to the case of the wiring layer on the surface side described above, such a process is repeated when there are three or more wiring layers, for example.

  Thereafter, the contact layer 30 for fixing the potential of the body region 28 of the MOSFET 12 formed on the front surface side is provided on the back surface side of the single crystal silicon layer 4 as shown in FIG. The semiconductor integrated circuit device 11 having the above-described configuration can be obtained.

  In the present embodiment, when the contact layer 30 is formed (see FIG. 7B), the activation of the ion-implanted region is performed following the ion implantation. The activation can be performed simultaneously with the formation of the source region 15 and the drain region 16 of the MOSFET 12 to be formed.

According to the manufacturing method of the semiconductor integrated circuit device 11 of the present embodiment described above, before forming the MOSFET 12 and the wirings (211, 212) on the surface side of the SOI substrate 5, a predetermined position of the substrate 5 is formed from the surface side. Since the contact layer 30 is formed by ion implantation, for example, after forming the MOSFET 12 and the wirings (211, 212) on the front surface side of the SOI substrate 5, contact is made from the back surface side to a predetermined position on the substrate 5. Compared with the method in which the layer 30 is formed by ion implantation, the thermal influence upon activation on the wirings (211 and 212) made of a material having low heat resistance formed on the surface side of the substrate 5 is suppressed. can do.
Further, as described above, it is possible to manufacture a semiconductor integrated circuit device having a configuration in which an increase in drain current due to fluctuations in the threshold value of the MOSFET 12 is suppressed.

  The configuration shown in FIG. 5 and the configuration shown in FIG. 12 can be combined to form a semiconductor integrated circuit device. In this case, as the wiring on the back surface side of the single crystal silicon layer 4, a wiring connected to the active layer (drain region 16) of the MOSFET 12 and a wiring connected to the contact layer 30 are provided independently.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1A to 1B are manufacturing process diagrams (part 1) showing an embodiment of a method for manufacturing a semiconductor integrated circuit device of the present invention. C to D are manufacturing process diagrams (part 2) illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention. EF is a manufacturing process diagram (part 3) illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention; FIG. GH is a manufacturing process figure (4) which shows one Embodiment of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic sectional drawing which shows one Embodiment of the semiconductor integrated circuit device of this invention. It is a schematic sectional drawing (the 1) which shows other embodiment of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic sectional drawing (the 2) which shows other embodiment of the manufacturing method of the semiconductor integrated circuit device of this invention. FIGS. 8A to 8C are manufacturing process diagrams (part 1) illustrating another embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention. FIGS. D to E are manufacturing process diagrams (part 2) illustrating another embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention. FG is a manufacturing process diagram (part 3) illustrating another embodiment of the method of manufacturing a semiconductor integrated circuit device of the present invention; FIG. FIG. 10 is a manufacturing process diagram (Part 4) illustrating another embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention; It is a schematic sectional drawing which shows other embodiment of the semiconductor integrated circuit device of this invention. It is a schematic sectional drawing which shows the structure of the conventional semiconductor integrated circuit device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,11 ... Semiconductor integrated circuit device, 2 ... Support substrate, 3 ... Embedded oxide film (BOX layer), 4 ... Single crystal silicon layer, 5 ... SOI substrate, 6 ... Element Isolation region, 7 ... element formation region, 8 ... connection layer, 9 ... hole, 10 ... polycrystalline silicon, 12 ... MOSFET, 13 ... gate insulating film, 14 ... Gate electrode, 15 ... source region, 16 ... drain region, 19 ... etching stopper film, 21 ... wiring layer (front side), 22 ... wiring layer (back side), 23 .. Interlayer insulating film, 24 ... contact wiring, 25 ... flattening film, 26 ... adhesive layer, 27 ... support substrate, 30 ... contact layer

Claims (5)

Forming a connection layer reaching the back side from the front side to the semiconductor layer;
Forming a transistor on the surface side of the semiconductor layer where the connection layer is formed , and directly connecting the connection layer and the drain region of the transistor;
Forming a first wiring layer on the surface side of the semiconductor layer in which the transistor is formed , connected to the source region of the transistor;
And forming a second wiring layer on the back side of the semiconductor layer by connecting to the connection layer. A method for manufacturing a semiconductor integrated circuit device. For a substrate in which a semiconductor layer is laminated on a support substrate via an insulating film,
Forming a connection layer reaching from the front surface side to the back surface side in the semiconductor layer;
Forming a transistor on the surface side of the semiconductor layer where the connection layer is formed , and directly connecting the connection layer and the drain region of the transistor;
Forming a first wiring layer on the surface side of the semiconductor layer in which the transistor is formed , connected to the source region of the transistor;
Then, removing the support substrate,
Forming a second wiring layer by connecting to the connection layer on the back side of the semiconductor layer after the support substrate is removed .   3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the connection layer is formed by forming a hole in the semiconductor layer and embedding a semiconductor layer to which an impurity is added in the hole.   The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the connection layer is formed by ion implantation into the semiconductor layer from a surface side. For a substrate on which a semiconductor layer is formed on a support substrate via an insulating film,
Forming an impurity region for fixing the potential of the semiconductor layer only on the back surface side of the semiconductor layer by ion implantation from the surface side of the semiconductor layer;
Forming a transistor on the surface side of the semiconductor layer in which the impurity region is formed ;
Forming a first wiring layer on the surface side of the semiconductor layer, connected to the source region of the transistor;
Removing the support substrate;
Forming a second wiring layer connected to the impurity region on the back surface side of the semiconductor layer. A method for manufacturing a semiconductor integrated circuit device.

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