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JPS6422067A - Double diffusion type insulated-gate field effect transistor - Google Patents

Double diffusion type insulated-gate field effect transistor

Info

Publication number
JPS6422067A
JPS6422067A JP62178381A JP17838187A JPS6422067A JP S6422067 A JPS6422067 A JP S6422067A JP 62178381 A JP62178381 A JP 62178381A JP 17838187 A JP17838187 A JP 17838187A JP S6422067 A JPS6422067 A JP S6422067A
Authority
JP
Japan
Prior art keywords
diffusion layer
layer
channel forming
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62178381A
Other languages
Japanese (ja)
Inventor
Kazuaki Onishi
Yukinobu Miwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62178381A priority Critical patent/JPS6422067A/en
Publication of JPS6422067A publication Critical patent/JPS6422067A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
    • H10D84/144—VDMOS having built-in components the built-in components being PN junction diodes in antiparallel diode configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the protruding of a second conductivity type diffusion layer of high concentration, and the decrease of breakdown strength due to the curvature of a depletion layer, by forming the second conductivity type diffusion layer of high concentration to the same depth as a channel forming base region or the shallower depth. CONSTITUTION:In a channel forming diffusion layer in the operating part (cell) of a D-MOSFET, a P<+> layer 51 is formed to the same depth as the channel forming diffusion layer 4, or the shallower depth, by the following process; after the channel forming diffusion layer 41 is formed, an aperture is partially made by using photolithography method or the like, impurity is implanted by using ion implation method or the like, and then heat-treating is preformed. The P<+> layer 51 can be used as a built-in diode together with an N-layer 2. Further, owing to the shallow diffusion layer, the temperature becomes higher as compared with prior devices, and the forward direction voltage characteristics are improved.
JP62178381A 1987-07-17 1987-07-17 Double diffusion type insulated-gate field effect transistor Pending JPS6422067A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62178381A JPS6422067A (en) 1987-07-17 1987-07-17 Double diffusion type insulated-gate field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62178381A JPS6422067A (en) 1987-07-17 1987-07-17 Double diffusion type insulated-gate field effect transistor

Publications (1)

Publication Number Publication Date
JPS6422067A true JPS6422067A (en) 1989-01-25

Family

ID=16047497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62178381A Pending JPS6422067A (en) 1987-07-17 1987-07-17 Double diffusion type insulated-gate field effect transistor

Country Status (1)

Country Link
JP (1) JPS6422067A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0671769A2 (en) * 1994-03-10 1995-09-13 Nippondenso Co., Ltd. Insulated gate field effect transistor
WO2002082553A1 (en) * 2001-04-04 2002-10-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149056A (en) * 1983-02-15 1984-08-25 Nissan Motor Co Ltd Vertical metal oxide semiconductor transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149056A (en) * 1983-02-15 1984-08-25 Nissan Motor Co Ltd Vertical metal oxide semiconductor transistor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0671769A2 (en) * 1994-03-10 1995-09-13 Nippondenso Co., Ltd. Insulated gate field effect transistor
EP0671769A3 (en) * 1994-03-10 1999-05-06 Denso Corporation Insulated gate field effect transistor
WO2002082553A1 (en) * 2001-04-04 2002-10-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPWO2002082553A1 (en) * 2001-04-04 2004-07-29 三菱電機株式会社 Semiconductor device
JP4837236B2 (en) * 2001-04-04 2011-12-14 三菱電機株式会社 Semiconductor device
US8183631B2 (en) 2001-04-04 2012-05-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US8692323B2 (en) 2001-04-04 2014-04-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with peripheral base region connected to main electrode

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