JPS6413757A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve characteristics at the time when a power supply is turned ON by a method wherein a first transistor is kept conductive for a fixed time after the power supply is turned ON, an output terminal for a substrate bias generating circuit is clamped forcibly at 0V a second transistor is kept conductive after the fixed time passes and the working of the substrate bias generating circuit is transmitted to the output terminal. CONSTITUTION:When a power supply VCC is turned at the time S0, the power supply VCC rises toward a specified potential level during the time from the time S0 to the time S2. Potential VP1 at a node P1 follows to the rise of the power supply VCC by the capacitive coupling of a capacitor CA after the time S0. Substrate bias potential VBB is also elevated gradually by the capacitive coupling of a parasitic capacitor CT. When potential VP1 exceeds the threshold voltage VTH of a transistor Q1 at the time S1, the transistor Q1 becomes conductive, thus short-circuiting a VSS wiring 2 and a VBB wiring 4, then forcibly clamping potential VBB at 0V. A pulse signal POR rises at the time S4 and exceeds the threshold voltage of a transistor Q2 up to the time S5, thus making the transistor Q2 conductive. Accordingly, characteristics at the time when the power supply is turned ON can be improved.