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JPS6413479A - Test system for integrated circuit - Google Patents

Test system for integrated circuit

Info

Publication number
JPS6413479A
JPS6413479A JP62170451A JP17045187A JPS6413479A JP S6413479 A JPS6413479 A JP S6413479A JP 62170451 A JP62170451 A JP 62170451A JP 17045187 A JP17045187 A JP 17045187A JP S6413479 A JPS6413479 A JP S6413479A
Authority
JP
Japan
Prior art keywords
inputted
signal
gate
driver control
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62170451A
Other languages
Japanese (ja)
Other versions
JPH0746123B2 (en
Inventor
Nobukazu Kirigatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62170451A priority Critical patent/JPH0746123B2/en
Publication of JPS6413479A publication Critical patent/JPS6413479A/en
Publication of JPH0746123B2 publication Critical patent/JPH0746123B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To reduce collisions on a bus being tested by limiting the supply of a driver control signal outputted from a driver control means to a two-way bus driver. CONSTITUTION:When test data is inputted to the input pin of a LSI 201 to advance operation by one cycle in synchronism with a system clock signal SC, a signal for driver control inputted to the D terminal of a FF 211 is latched and inputted to a 1st input terminal of a NAND gate 221. A FF 223 latches scan-in data latched by an FF 243 in synchronism with a next signal SC, so 0 or 1 is inputted to a 2nd input terminal as the output of the FF 223. When the input value is 1, an output signal corresponding to the signal inputted to the 1st input terminal is inputted from the gate 221 to a two-way bus driver 231. Therefore, when 0 is inputted to the gate 221, a driver control signal inputted to the gate 221 from the FF 221 is made ineffective.
JP62170451A 1987-07-08 1987-07-08 Integrated circuit test method Expired - Fee Related JPH0746123B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170451A JPH0746123B2 (en) 1987-07-08 1987-07-08 Integrated circuit test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170451A JPH0746123B2 (en) 1987-07-08 1987-07-08 Integrated circuit test method

Publications (2)

Publication Number Publication Date
JPS6413479A true JPS6413479A (en) 1989-01-18
JPH0746123B2 JPH0746123B2 (en) 1995-05-17

Family

ID=15905174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170451A Expired - Fee Related JPH0746123B2 (en) 1987-07-08 1987-07-08 Integrated circuit test method

Country Status (1)

Country Link
JP (1) JPH0746123B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5143785A (en) * 1990-08-20 1992-09-01 Minnesota Mining And Manufacturing Company Cyanate ester adhesives for electronic applications
US5457149A (en) * 1990-06-08 1995-10-10 Minnesota Mining And Manufacturing Company Reworkable adhesive for electronic applications

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114258A (en) * 1985-11-13 1987-05-26 Nec Eng Ltd Large-scale integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114258A (en) * 1985-11-13 1987-05-26 Nec Eng Ltd Large-scale integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457149A (en) * 1990-06-08 1995-10-10 Minnesota Mining And Manufacturing Company Reworkable adhesive for electronic applications
US5143785A (en) * 1990-08-20 1992-09-01 Minnesota Mining And Manufacturing Company Cyanate ester adhesives for electronic applications

Also Published As

Publication number Publication date
JPH0746123B2 (en) 1995-05-17

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees