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JPS6410122A - S/d converter - Google Patents

S/d converter

Info

Publication number
JPS6410122A
JPS6410122A JP16531087A JP16531087A JPS6410122A JP S6410122 A JPS6410122 A JP S6410122A JP 16531087 A JP16531087 A JP 16531087A JP 16531087 A JP16531087 A JP 16531087A JP S6410122 A JPS6410122 A JP S6410122A
Authority
JP
Japan
Prior art keywords
data
bit
synchro
zero
correcting value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16531087A
Other languages
Japanese (ja)
Inventor
Kazuo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16531087A priority Critical patent/JPS6410122A/en
Publication of JPS6410122A publication Critical patent/JPS6410122A/en
Pending legal-status Critical Current

Links

Landscapes

  • Arrangements For Transmission Of Measured Signals (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)

Abstract

PURPOSE:To easily decide a zero-point correcting value for synchro data by providing a means which adds the zero-point correcting value for the synchro data in output data to an S/D converter which converts the synchro data into digital data. CONSTITUTION:The S/D converter 1 inputs the synchro data d0 and outputs the digital data d1, which is held in a register 2. This data d1 is 12-bit data. A constant setting circuit 4, on the other hand, sets a 4-bit code corresponding to the zero-point correcting value for the synchro data and outputs it as digital data d2. The two data d1 and d2 are put together into d3 by a composing circuit 3. The 12-bit part ai of the composite data d3 from the 15th bit to the 4th bit is the same as the data d1 and indicates a synchro digital converted value. The 4-bit part (z) from the 3rd bit to the 0th bit is a code corresponding to the zero-point correcting value.
JP16531087A 1987-07-03 1987-07-03 S/d converter Pending JPS6410122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16531087A JPS6410122A (en) 1987-07-03 1987-07-03 S/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16531087A JPS6410122A (en) 1987-07-03 1987-07-03 S/d converter

Publications (1)

Publication Number Publication Date
JPS6410122A true JPS6410122A (en) 1989-01-13

Family

ID=15809903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16531087A Pending JPS6410122A (en) 1987-07-03 1987-07-03 S/d converter

Country Status (1)

Country Link
JP (1) JPS6410122A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011105151A1 (en) 2010-02-26 2011-09-01 積水メディカル株式会社 Composition for plasma and serum separation, and container for blood testing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011105151A1 (en) 2010-02-26 2011-09-01 積水メディカル株式会社 Composition for plasma and serum separation, and container for blood testing

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