JPS6388657A - Memory device - Google Patents

Abstract

PURPOSE:To speed up the processing speed by rotationally shifting an N-bit data from a memory element then outputting is based on a bit address in case of reading a data, and in case of writing the data, rotationally shifting an N-bit data and inputting it to the memory element. CONSTITUTION:A selection means (for instance a decoder circuit 3) selects N-pieces of memory element from among the memory elements (2N-pieces) of first and second memories 1, 2 based on address information such as the one bit in low order of a word address, and a bit address. In case of reading the data, a first shifting circuit 5 rotationally shifts the N-bit data from the N-pieces of memory elements selected by a selection means 3, based on the bit address in the address information, then outputs the result. In case of writing the data, a second shifting circuit 6 rotationally shifts an input N-bit data based on the bit address then inputs the data to a memory element selected by the selection means 3. In such a way, N-pieces of bits leading by an arbitrary bit can be all at once accessed, hence the processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory device, and particularly to a memory device that can be accessed in units of words starting from an arbitrary bit.

(Prior Art) Conventionally, in a memory device connected to a CPU, one address is assigned to each CPU instruction processing unit (hereinafter, this unit is called a word), for example, every 8 bits, 16 bits, or 32 bits. . Therefore, the CPU accesses the memory device word by word by specifying an address.

Even when used in the above memory devices, such as bitmap memory that handles image data whose basic unit of data is not fixed, in order to process the necessary bits, find the address to which the bit belongs and access it in word units. and took the necessary steps.

(Problems to be Solved by the Invention) However, in the conventional memory device, when processing data spanning between words, each word must be accessed and processed separately, which increases the number of accesses. increases, causing a decrease in processing speed.

The present invention solves the above-mentioned problem of boundaries between words, makes it possible to access one word following any specified bit at a time, increases processing speed, and realizes memory with a simple circuit configuration. The purpose is to provide equipment.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a memory device that performs reading and writing once in units of N bits.
a) The first memory element is composed of N memory elements each having a 1-bit width memory space, and stores data when the word address is an even number among address information including a word address and a bit address indicating the first bit position. memory, (b)
(C) a second memory consisting of N memory elements having a 1-bit width memory space and storing data when the word address is an odd number; (C) based on the address information;
selection means for selecting N memory elements from the memory elements of the first and second memories; (d) selecting N memory elements from the memory elements selected by the selection means based on the bit address;
(e) a first shift means for rotating and outputting bit data; (e) a first shift means for rotationally shifting and outputting bit data;
a second shifting means for rotationally shifting input N-bit data based on the bit address, and (f
) A generating means for generating addresses of the first and second memories based on the word address.

In a preferred embodiment, the selection means selects a memory element based on the lower 1 bit of the word address and the bit address, and the creation means supplies the bits of the word address excluding the lower 1 bit as an address to the second memory. At the same time, the first address is the sum of the bits excluding the lower 1 bit of the word address and the lower 1 bit.
It supplies the memory of

(Operation) According to the present invention, since the memory device is configured as described above, the technical means operates as follows.

The creation method is based on the word address of the address information,
Work to create the first and second memory addresses.
. For example, Pino l excluding the lower 1 bit of the word address
- is used as an address to supply the second memory, and the bits except the lower 1 bit of the word address and the lower 1
It works to supply the sum of the bits and bits as an address to the first memory. The selection means (for example, a decoder circuit) selects N memory elements from among the memory elements (2N pieces) of the first and second memories based on the address information, for example, the lower 1 bit of the word address and the bit address. to work. In the case of reading data, the first shifting means operates to rotationally shift and output N-bit data from the N memory elements selected by the selection means based on the bit address of address + fftft. . In the case of writing data, the second shifting means operates to rotationally shift and input the input N-bit data to the memory element selected by the selection means based on the bit address. In this way, with a simple configuration, N bits (one word) starting with an arbitrary bit can be accessed at once.

Therefore, since the processing speed is improved, the problems of the prior art described above can be solved.

(Embodiment) FIG. 1 is a configuration diagram of a memory device showing an embodiment of the present invention.
2 is a diagram showing the correspondence between the structure of address information and memory used in this embodiment. To simplify the explanation here,
The case where 1 word of 4 bits of data is accessed is shown.

In FIG. 1, 1 is an even memory that is made up of four memory elements each having a 1-bit width memory space and stores even words of data, and 2 is an even memory 4 that has a 1-bit width memory space like the even memory 1. This is an odd memory that stores odd words of data.

3 is a decoder circuit composed of a ROM, for example, and the lower 3 bits of address information (A21 AH + Ao)
Therefore, all memory elements 8 of even memory 1 and odd memory 2
A selection signal for selecting four memory elements from among the four memory elements is output from the output terminal (Yo=Y7) to the chip select terminal (CS) of each memory element. This is a full adder that creates the address of even memory 1 by adding the other pin (A2) and this other pin (Am=Ax), and outputs the created address to the address terminal (A) of the even memory. are doing. odd memory 2
To the address terminal (A) of the word address, a value (Am-A3) excluding the lower 1 bit (A?) of the word address is input as an address. 5 inputs a total of 4 bits of data input from the output terminals (Do) of the memory elements of even memory 1 and odd memory 2 to the lower 2 bits of address information A 1
+ Rotationally shift only the bit indicated by AO (bit address) and data buses D4 to D! This is a shift circuit for reading. 6 is the 4-bit data input from data buses D4 to D, bit address A11 A
This is a write shift circuit that rotationally shifts the bit indicated by O and inputs the result to the input terminals (Dt) of the memory elements of the even memory 1 and the odd memory 2. These shift circuits 5 and 6 are realized, for example, by barrel shifters that can shift an arbitrary number of pits at one time.

As shown in FIG. 2, the address information input from the CPU etc. is composed of a word address Am-A3 r A2 and a inhibit address Al r AO. A2 (lower one bit of the word address) indicates whether to start accessing from an even word (that is, even memory 1) or an odd word (that is, odd memory 2). Further, bit address 0 A1, A indicates from which bit of even word r or odd word r one word should be accessed. That is, this indicates the first bit position.

Here, considering the addresses to be given to the even memory 1 and the odd memory 2, the addresses differ depending on whether the access is started from an even word or an odd word. This address relationship is shown in FIGS. 3(a) and 3(b). Figure 3 (
As shown in Figure 3 (b), when accessing from a bit in an even word (A2 = 0), even memory 1, odd memory 2, jA<Am-A3 can be given as the address. ), when accessing from bits in odd words (A2=1), odd memory 2 has A.
m-A3 is fine, but for even number memory 1, Am-A3 plus 1 must be given as the address. Therefore, the full adder 4 gives Am = A3 plus A2 as the address of the even memory 1, and the address of the odd memory 2 is given as the address of the even memory 1.
It is sufficient to give Am ``'' A 3 as the address.

In this embodiment, the decoder circuit 4 generates a selection signal for selecting four necessary memory elements from a total of eight memory elements, an even memory 1 and an odd memory 2.

FIG. 4 shows 72 turns of this selection signal. The decoder circuit 3 generates a pattern as shown in FIG. 4 according to the values of the lower three bits A2 to AO of the address information (that is, the lower one bit of the word address and the bit address), and selects a pattern from among the eight memory elements. Enable only 4. For example, the third
To enable the shaded bits (i.e. memory elements) in figure (a), the lower three bits of address information eAz=0, A
1 ” 1 r AO = 1.Similarly, in the case of Fig. 3(b), the lower 3 bits are all “1”.
You can specify it by

When reading data from the four memory elements selected in this way, a READ signal is input to the shift circuit 5, and the bits specified by the bit address AI + Ao (lower two bits of address information) are read from the word Bit movement (rotational shift) is performed by the shift circuit 5 so that it is at the beginning of the file. For example, Figure 3 (,), (b)
In the case (hatched area), both bit addresses AI r
Since AO is specified as "1", "1" (i.e. "3"),
All you have to do is shift it by 3 bits. When writing data, the ITE signal is input to the shift circuit 6, and the shift circuit 6 shifts the bits so that the word (4 bits) of input data is input to a position that correctly corresponds to the selected memory element. (In the case of FIGS. 3(a) and 3(b), only 3 bits are shifted).

In this way, according to this embodiment, a word starting with an arbitrary bit can be accessed at once with a very simple structure, so the number of accesses to memory (1, 2) can be reduced and processing speed can be improved. We can expect that.

Furthermore, the number of memory elements can be reduced by using a recently developed memory in which writing can be controlled on a bit-by-bit basis. Furthermore, by adding a control bit and inputting it to the decoding circuit (3) and slightly changing the selection signal pattern, it is possible to access not only word units but also lengths such as 1/2 word, 1/4 word, etc. It becomes possible.

(Effects of the Invention) As described in detail above, according to the present invention, a word starting with an arbitrary bit can be accessed at once with a very simple configuration, so the number of memory accesses can be reduced and processing It can be expected that the speed will improve.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a memory device showing an embodiment of the present invention;
Figure 2 is a diagram showing the correspondence between the structure of address information and memories, Figures 3 (a) and (b) are illustrations of how to create addresses for even and odd memories, and Figure 4 is a diagram of the decoder circuit. FIG. 3 is a diagram showing a pattern of a selection signal. 1... Even number memory, 2... Odd number memory, 3... Decoder circuit, 4... Full adder, 5, 6... Shift circuit. Patent applicant Oki Electric Industry Co., Ltd. Patent application agent Patent attorney Megumi Yamamoto - Fu 1F No. 42

Claims (2)

[Claims] (1) In a memory device that performs one-time reading and writing in units of N bits, (a) It consists of N memory elements with a 1-bit width memory space, and includes a word address and a bit address indicating the first bit position. (b) A first memory that stores data when the word address is an even number among the address information; (b) consisting of N memory elements each having a 1-bit width memory space; (c) selection means for selecting N memory elements from the memory elements of the first and second memories based on the address information; (d) based on the bit address; (e) first shifting means for rotationally shifting and outputting N-bit data from the memory element selected by the selection means; (e) inputting N bits of data to the memory element selected by the selection means based on the bit address; A memory device comprising: second shifting means for rotationally shifting and inputting data; and (f) creating means for creating addresses of first and second memories based on the word address. (2) The selection means selects a memory element based on the lower 1 bit of the word address and the bit address, and the creation means supplies the bits excluding the lower 1 bit of the word address as an address to the second memory, 2. The memory device according to claim 1, wherein the sum of bits excluding the lower 1 bit of the word address and the lower 1 bit is supplied as an address to the first memory.