JPS6182252A - Memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a memory for converting a sequence of data words into another sequence of data words whose contents follow a first sequence as a function of a predetermined transformation ratio. and a reading method and memory. In particular, the invention relates to a memory and a method for using this memory to encode and decode data in the form of binary words.

OBJECTS OF THE INVENTION Accordingly, the present invention provides a means for selectively addressing 71 to 6x of memorized addressable cells that are addressable in a matrix along two vertical address directions determined by the matrix; and means for selectively writing and reading data according to the two address directions.

This memory stores data by writing data into the memory along a direction having a predetermined address, and a first memory having a different predetermined address.
This makes it possible to read data in a direction perpendicular to the direction.

The invention will be explained in more detail by way of example only in the following description with reference to FIG.

Embodiment A memory 1 includes a memory cell network 2 arranged here in an XY matrix of rows and columns of 16 cells. Therefore, in this embodiment, memory 1 is preferably used in a 16-bit word device, although other formats may also be used.

The memory cell network 2 is connected to a control unit 3 which applies X and Y addresses in two vertical directions and the data associated with these addresses in these two directions. are read out to or from the memory 1 along the line. For explanation purposes, (first
Arbitrarily assuming that the direction It is understood that it is placed.

This data circulates in the X and Y direction via input/output buses 4 and 5, which are connected to two transfer registers 6, 7, which are connected to a general-purpose system bus 8 which functions, for example, in time-division multiplexing of the data. communicate with.

The data stored vertically at addresses XO to X15 can be supplied via an output bus 9 to a logic unit 10 that performs logical processing on this data and the data on the input/output bus 5. The logic unit 1o has a mask/output bus 4 connected to the input/output bus 4 via a shunt connection 12.
Register 11 can also be used.

The control unit 3 includes two address generation circuits 13, 14 for addresses X and Y, a write/read address selection circuit 15, an X/Y selection circuit 16, a selection circuit 17 for the address direction, etc., for completing addressing. Two circuits 18 and 19 are provided for establishing the circuit.

The embodiment of FIG. 1 assumes that data is received by the receiver circuit 20 from some source (not shown) and is retained for use by the device. The receiver circuit 20 is connected to the general purpose system bus 8, which is connected to the ii! It is also connected to the control microprocessor 21. The control microprocessor 21 is connected to a ROM memory 22 in which the program of the control microprocessor 21 is stored. The control microbe 1 controller 21 is
For the program, it generates the memory data and addresses necessary for its operation and for decoding the input data, which is here assumed to be encoded.

Therefore, the control microprocessor 21 uses transfer registers 6.7 connected between the input/output buses 4 and 5 and the general-purpose system bus 8 to control the address generation circuits 13 to 1.
9, controls mask register 11, and controls data loading and insertion.

A general purpose system bus 8 has a program read only memory (ROM) 24 and an associated microprocessor 23.
The memory 24 is also connected to the memory 1 and processes the data decoded in the memory 1 for use in a specific utilization circuit (not shown).

For example, the receiver circuit 20 is connected by a Hertzian connection or a ΔC connection to a source that maintains the confidentiality of the data and allows the control microprocessor 21 to scramble the data according to a known program. This data is then easy to format and decode to reconfigure it so that it can be read and utilized by the microprocessor 23. For other uses, the receiving circuit 20
The purpose is to keep secret the program of transparent data sent to the memory 1 and to encode the data in the memory 1 by means of a control microprocessor 21, which is here used as a means for controlling the encoding.

In this case, the microprocessor 23 and peripheral devices (
(not shown) can reproduce the program in an encoding format that is incomprehensible to those who do not have that code.

FIG. 2 shows an example of a memory cell m of circuit wI2 in a hardwired circuit. As will be apparent to those skilled in the art, such networks can also be fabricated in integrated circuits in which each cell has identical characteristics. The base component of each memory cell m is, for example, a model 7474 sold by Texas Instruments.
” type flip-flop 25.This flip-flop
The flop 25 has an output terminal S and a clock terminal CL.

Each input of the flip-flop 25 is connected to a gate 26 and selectively connected to address lines AxmEc and Axml- for data input/output lines E/Sxm and E/Sym.

Ayml:c, ΔVmL can be connected to load or retrieve data. These address lines are connected to multiplexer 27, as shown in FIG. This multiplexer 27 forms part of the address generation circuits 13 and 14 of FIG.

Each part of the multiplexer 27 can be activated by the signal @L/EC of the write/read selection circuit 15.

The transfer of data is controlled by the signal CL on line 28.

This data can be processed in successive blocks of words, with a maximum number of words in each block being, for example, 16. To this end, each word is sequentially set in the network 2 in a predetermined direction by the X/Ym selection circuit 16.

The addresses at which this data is arranged can be increased or decreased within two preset ranges, and the distance between these ranges is the number of words in a given block.

For example, if you want to process 10 blocks of 5 words consecutively, these words can be arranged from address Y5 to address Y9 (increasing direction) or from address Y11 to address Y7 (decreasing direction). . Of course, all other range values and all other numbers of words (up to 16) can be used. It should be noted that these parameters can be changed from the first group of words to the next, all as a function of the required encoding or decoding.

In order to determine the address value or range in the processing of each word block, the control micros = 11- may be preloaded by the processor 21 for the processing of the word block. Possible [Parameter 4 circuit 18
and 19 are used.

These circuits 18 and 19 (FIG. 3) are connected to register 29 (
It is connected to a configuration consisting of a counter 30) and a comparator 31. Register 29 and counter 30 are loadable from circuits 18 and 19, and the encoding and encoding inputs of counter 30 are connected to control circuit 17 in the direction of address progression.

The coincidence output 32 of the comparator 31 is sent to the control microprocessor 2.
1 and notifies the control microprocessor 21 that the advanced address has reached a limit value.
- Of course, the above idea can also be applied to reading and writing data. Encoding and decoding consists of loading or reading successive blocks of words in a first direction and then in the other direction.

FIG. 5 is a flowchart of an encoding cycle in which the full capacity of memory 1 is used and one block is 16 words.

The first process (process 32a) is performed by the control microprocessor 21
This time control includes the loading of parameters necessary for writing one block of data in the control unit 3. These parameters are based on the selected axis (here Y),
The addressed terminal (Δ-〇 and B=15>) and the direction in which the address advances (Y15 to YO), that is, counter 3
This is a down count by 0. At the end of this one code, the first word is retrieved from the receiving circuit 20 by the control microprocessor 21 (process 33) and stored at address Y15 in the memory 1 (process 34). This process 34 is repeated until the address becomes O (decision 35. process 36). When this condition is satisfied, comparator 32 combines the contents of register 29 (here equal to O) with register 3
Since the contents of 0 (count drops to 0) indicate equality, an end-of-cycle signal is provided to the control microprocessor 21 (processor 1!J!37).

In the example described above, it has been assumed that network 2 completely fills the 16 addresses with 16 address words. By programming the register 29 with a different value and/or starting from an address other than the starting address of the network 2, it is also possible to store blocks with a number of words less than 16.

When the end-of-cycle signal occurs, the control microprocessor 21 controls the supply of data words to the receiving circuit 20 and loads other parameters into the control unit 3 (process 38).

In this case, the data stored in memory 1 is transferred to terminal A=0
, B-15 and a direction in which the addresses advance from x15 to xO. Thereafter, the microprocessor 23 is energized (operation 39) and receives a word block of data (here number 16) corresponding to reading out the memory cells of the network 2 in the X-axis direction; 23 is processing 40. Judgment 4
1 and processing 42, the corresponding data is sent to the microprocessor 23.
It can be sent continuously.

When the comparator 31 outputs a cycle end signal, this cycle is stopped and a new cycle can then be started (process 44). Of course, the data in this block is encoded (for example, even if the control microprocessor 23 simply reads it from the memory in which it is stored, it will result in an initially incomprehensible group of information. The data being written has been encoded in X1III according to an encoding key consisting of 16 words of writing.

It will be appreciated that the encoding key is capable of a wide variety of changes according to the addresses selected by the microprocessor program.

The encoded data can be used in any desired manner, such as cable transmission by Hertzian bundle or other methods, storage in memory, coding of programs, etc. Various applications of the invention will be apparent to those skilled in the art.

Of course, the encoding of the data can also be carried out in exactly the same way, so as to be encoded in a program using the memory 1 in the same way.

In the above, the explanation of the logical unit 10 is omitted.

This logic unit 10 is for obtaining auxiliary encoding and decoding of the eight logical operations performed on the data stored in the memory 1 and on the system input data. This logic unit 1° itself has a normal structure, and includes logic circuits OR, AND, N0T-AND, N T
(non-inverting), etc., and those functions are controlled by the control unit 3, and they are controlled by the circuit network 2.
is introduced into the device by the control microprocessor 21 after completing the data and before reading out this data.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a data encoding and decoding device having a memory according to the invention, and FIG. 2 is a block diagram of an embodiment of a cell of said memory in word wire connection, having an address multiplexer. 3 is a block diagram of a (memory) control unit; FIG. 4 is a timing diagram illustrating a memory write cycle; and FIG. 5 is a flow diagram of an encoding cycle performed by a memory according to the invention. 2... Matrix, 3... Control units 1~. 1o
... logic]-nit, 11 ... mask register,
17... selection circuit, 21 river control microprocessor,
22.24...Memory, 23...Microprocessor, 25...Flip-flop, 26...Gate, 27...Multiplexer, 2...Registers, 3
0...Counter, 31...Comparator.

Claims (8)

[Claims] (1) In a memory with a matrix of m memory cells addressable in a matrix, two perpendicular address directions (X
, Y), and means for writing and reading data further selected according to the vertical direction. (2) A memory according to claim 1, wherein each row and column of m memory cells of said matrix is provided with respective condition means for transferring address and data bits for said m memory cells of said matrix. The connected read address lines (AxmL, AymL), write address lines (AxmEc, AymEc), and data input/output lines (E/Sxm, E/Sym) are connected as address means so as to be read. memory. (3) A memory according to claim 2, in which each of the m memory cells of the matrix comprises a flip-flop having an input address E and an output address S, the input address being connected to a first transfer gate. is connected to the data input/output line (E/Sym) of the column by the second transfer gate, and connected to the data input/output line (E/Sym) of the row by the second transfer gate.
Further, the first and second transfer gates have respective transfer control terminals connected to the write address line (AymEc) of the column and the write address line (AxmEc) of the row, respectively. - the output address S of the cell is connected to the input/output line (E/Sym) of the column by a third transfer gate, and connected to the data input/output line (E/Sxm) of the row by a fourth transfer gate; A memory characterized in that the third and fourth transfer gates have transfer and control terminals respectively connected to the read address lines (AymL, AxmL) of the matrix. (4) In the memory according to any one of claims 2 and 3, an enable connected to the write and read address lines of the matrix and for selecting an address of the matrix. Input (VaLx, V
aLy) and an enable input (L/E) for selecting said write and read address lines. (5) In the memory according to any one of claims 1 to 4, a certain row and/or column that are consecutive among the rows and/or columns of the matrix.
1. A memory comprising means for specifying address ranges for write and read cycles only for columns using row or column addresses. (6) The memory according to claim 5, wherein the means for defining an addressing range includes a register for storing an address value that is one within the address range for a particular write and read cycle; A count circuit that follows the progress of the address value based on the address value, and a comparator that compares the contents of the register with the contents of the count circuit and generates a cycle end signal when the contents are equal. A memory characterized by: (7) In the memory according to claim 6, the count circuit is an up/down counter, and includes a control circuit for the direction of progression of the address value, and controls the up/down of the count circuit. A memory characterized in that it is connected to an input. (8) The memory according to any one of claims 1 to 7, which includes a logic circuit according to data read from the memory so as to perform logical processing according to input data. A memory comprising at least one.