JPS638620B2 - - Google Patents
Info
- Publication number
- JPS638620B2 JPS638620B2 JP57168932A JP16893282A JPS638620B2 JP S638620 B2 JPS638620 B2 JP S638620B2 JP 57168932 A JP57168932 A JP 57168932A JP 16893282 A JP16893282 A JP 16893282A JP S638620 B2 JPS638620 B2 JP S638620B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- ceramic
- grid array
- view
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 description 21
- 239000004020 conductor Substances 0.000 description 7
- 238000002844 melting Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は連続打抜形成されるインナーパターン
を信号線接続用のパターン導体とするいわゆるピ
ングリツドアレイ型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a so-called pin grid array type semiconductor device in which an inner pattern formed by continuous punching is used as a pattern conductor for connecting signal lines.
(b) 技術の背景
通常高信頼性を要求される半導体装置は外部雰
囲気の影響を受けない耐湿性のハーメチツクシー
ル構造とするのが一般的であり、半導体素子を収
容したセラミツク容器の封止は蓋板（キヤツプ）
を金錫（Au―Su）、鉛錫半田（Pb―Sn）、低融点
ガラス、シーム抵抗溶接等により接着して行なわ
れる。気密封止形パツケージには主としてサイド
ブレース形、サーデイツプ形、ピングリツドアレ
イ形があり、何れも一長一短がある。半導体素子
の高密度高集積化されるに従い外部との信号線接
続用端子数は増加しこれに伴い多ピン構成のパツ
ケージが有利となる。更にコスト低減のための封
止構造について研究開発がなされている。(b) Background of the technology Semiconductor devices that require high reliability generally have a moisture-resistant hermetic seal structure that is not affected by the external atmosphere. The stop is the lid plate (cap)
This is done by bonding with gold-tin (Au-Su), lead-tin solder (Pb-Sn), low melting point glass, seam resistance welding, etc. There are three main types of hermetically sealed packages: side brace type, third dip type, and pin grid array type, all of which have advantages and disadvantages. As semiconductor devices become more densely integrated, the number of terminals for connecting signal lines to the outside increases, and as a result, packages with a multi-pin configuration become advantageous. Furthermore, research and development is being conducted on sealing structures to reduce costs.
(c) 従来技術と問題点
第１図は従来のピングリツドアレイ形半導体装
置を示す断面図である。多数個の外部端子３を周
辺部に配設したセミラツク基板１上に半導体素子
２を塔載し、半導体素子２の入出力信号端子とセ
ラミツク基板１に設けたメタライズ導体とをワイ
ヤボンデング接続した後、金属又はセラミツクキ
ヤツプ４を金一錫シール５等で封止する。半導体
素子２の入出力信号端子はワイヤ６及びメタライ
ズ導体を介して外部端子３に電気的に結合され
る。このように構成されるピングリツドアレイ半
導体装置は部品構成が複雑であり例えばメタライ
ズ導体を被膜形成したセミラツクを積層して焼成
する基板形成及び外部端子３の埋込固定半導体素
子２をセラミツク基板１へのマウンド実装或いは
キヤツプ４の封止等生産プロセスも多岐にわたり
量産化自動化されにくい。これに対して内部配線
にリードフレームを用い、セラミツク基板上に半
導体素子をマウントし低融点ガラスでセラミツク
キヤツプをシールするサーデイツプ形がある。(c) Prior Art and Problems FIG. 1 is a sectional view showing a conventional pin grid array type semiconductor device. A semiconductor element 2 is mounted on a semi-racqueous substrate 1 on which a large number of external terminals 3 are arranged around the periphery, and input/output signal terminals of the semiconductor element 2 and metallized conductors provided on the ceramic substrate 1 are connected by wire bonding. After that, the metal or ceramic cap 4 is sealed with a gold-tin seal 5 or the like. The input/output signal terminals of the semiconductor element 2 are electrically coupled to the external terminals 3 via wires 6 and metallized conductors. The pin grid array semiconductor device constructed in this way has a complicated component structure, and for example, the substrate is formed by laminating and firing semi-lacquer coated with a metallized conductor, and the embedded fixed semiconductor element 2 of the external terminal 3 is placed on the ceramic substrate 1. The production processes, such as mound mounting and sealing of the cap 4, are diverse and difficult to automate mass production. On the other hand, there is a ceramic type that uses a lead frame for internal wiring, mounts a semiconductor element on a ceramic substrate, and seals the ceramic cap with low-melting glass.
第２図は従来のサーデイツプ形半導体装置を示
す断面図である。セラミツク基板７に半導体素子
８を搭載し、リードフレーム９で構成されるパタ
ーン導体と半導体素子８の信号端子をワイヤボン
デング接続し、パターン導体及びセラミツクキヤ
ツプ１０を低融ガラス１１でシールする。このよ
うに構成されるサーデイツプ形半導体装置は量産
化に有利である反面外部リードピン１２はパター
ン導体をなすリードフレーム９と一体的に形成さ
れるデユアルイン型であるため、多ピン構成が要
求される大容量素子には不向きであり、また半導
体容器を大型化し多ピン構成とすることは装置へ
の実装密度を低減させ好ましくない。 FIG. 2 is a sectional view showing a conventional deep dip type semiconductor device. A semiconductor element 8 is mounted on a ceramic substrate 7, a pattern conductor constituted by a lead frame 9 and a signal terminal of the semiconductor element 8 are connected by wire bonding, and the pattern conductor and the ceramic cap 10 are sealed with a low melting glass 11. Although the third-deep type semiconductor device configured in this way is advantageous for mass production, it is a dual-in type in which the external lead pins 12 are integrally formed with the lead frame 9 that forms a pattern conductor, so it is suitable for large scale devices that require a multi-pin configuration. It is unsuitable for capacitive elements, and increasing the size of the semiconductor container and having a multi-pin configuration is undesirable because it reduces the packaging density in the device.
(d) 発明の目的
本発明は上記の点に鑑み、外部リード端子を打
抜成形されるインナーパターン（リードフレー
ム）の一端に固定し、セラミツク容器にガラス融
着する量産化に有利なピングリツドアレイ形半導
体装置の提供を目的とする。(d) Purpose of the Invention In view of the above-mentioned points, the present invention provides a pingrid, which is advantageous for mass production, in which an external lead terminal is fixed to one end of an inner pattern (lead frame) to be punched and formed, and glass is fused to a ceramic container. The purpose is to provide door array type semiconductor devices.
(e) 発明の構成
上記目的は、ピングリツドアレイ型パツケージ
の基板および蓋板と、該基板上にガラス層を介し
て配置された金属板を打ち抜いて形成したリード
フレームからなる内部配線と、該基板上に固着し
た半導体チツプとを有し、該内部配線の両端はそ
れぞれ該半導体チツプおよび該基板に埋め込まれ
たピンに電気的に接続され、該基板と該蓋板はガ
ラス層で融着して封止されている半導体装置によ
り達成される。(e) Structure of the Invention The above object is to provide a substrate and a lid plate of a pin grid array type package, an internal wiring made of a lead frame formed by punching out a metal plate placed on the substrate with a glass layer interposed therebetween; a semiconductor chip fixed on the substrate, both ends of the internal wiring are electrically connected to the semiconductor chip and a pin embedded in the substrate, respectively, and the substrate and the lid plate are fused together with a glass layer. This is achieved by a semiconductor device that is sealed in a sealed manner.
(f) 発明の実施例 以下本発明の実施例を図面により詳述する。(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第３図は本発明の一実施例であるインナーパタ
ーンを示す平面図、第４図はインナーパターンに
外部リードを取付けた断面図である。鉄ニツケル
合金（Fc―Ni）等でなるフレーム２１に所定の
パターン２２をプレス形成しその一端２２ａに同
一素材又はコバルト合金（Fe―Ni―Co）の外部
リード２３（第４図）をスポツト溶接等により固
定する。第４図に示すように外部リード２３に頭
部２３ａを設けパターン２２の一端２２ａに設け
たリード挿入孔２２ｂに係止させ垂直に位置出し
後溶接により固定する。またパターン２２の先端
２２ｃにはアルミ又は金等の膜を形成しワイヤボ
ンデングを容易にする。 FIG. 3 is a plan view showing an inner pattern according to an embodiment of the present invention, and FIG. 4 is a sectional view showing an outer lead attached to the inner pattern. A predetermined pattern 22 is press-formed on a frame 21 made of iron-nickel alloy (Fc-Ni) or the like, and an external lead 23 (Fig. 4) made of the same material or cobalt alloy (Fe-Ni-Co) is spot-welded to one end 22a. Fix it by etc. As shown in FIG. 4, the external lead 23 is provided with a head 23a, which is engaged with a lead insertion hole 22b provided at one end 22a of the pattern 22, and after being vertically positioned, is fixed by welding. Further, a film of aluminum or gold is formed on the tip 22c of the pattern 22 to facilitate wire bonding.
第５図のイ，ロ図は本発明の一実施例であるセ
ラミツク基板を示す構成図でありイは構成を説明
するための分解図、ロは組立断面図である。外部
リード２３を固定したインナーパターン２２と外
部リード２３に対応して貫通孔２４を備えた低融
点ガラスのプレフオーム２５及び同様に貫通孔２
６を設けたセラミツクベース２７によりセラミツ
ク基板２８を構成しプレフオーム２５を加熱融解
させてセラミツクベース２７に外部リード２３を
固定させるものである。 5A and 5B are configuration diagrams showing a ceramic substrate according to an embodiment of the present invention, A is an exploded view for explaining the configuration, and B is an assembled sectional view. An inner pattern 22 to which external leads 23 are fixed, a low melting point glass preform 25 having through holes 24 corresponding to the external leads 23, and similarly through holes 2.
A ceramic substrate 28 is constituted by a ceramic base 27 provided with a preform 25, and an external lead 23 is fixed to the ceramic base 27 by heating and melting the preform 25.
第６図は本発明の一実施例であるピングリツド
アレイ形半導体装置を示す断面図である。 FIG. 6 is a sectional view showing a pin grid array type semiconductor device which is an embodiment of the present invention.
セラミツク基板２８上のプレフオーム２５に図
のように半導体素子２９を搭載しプレフオーム２
５より更に融点の低いガラス部材で熱融着固定す
る。これは先に融着した外部リード２３の接着強
度に影響を与えないための配慮である。しかる後
に半導体素子２９の信号線接続用パツドとインナ
パターン２２の先端部２２ｂ（第２図、第３図参
照）をワイヤ３０でボンデング接続し、内側を凹
状に形成したセラミツクキヤツプ３１でガラス封
止し第３図で示すフレーム２１とパターン２２と
を接続する接続部２１ａを切断し外部リード２３
を半田デイツプ等で表面処理する。このように構
成する半導体装置であつて従来のピングリツドア
レイ形に比しセラミツク基板形成及びリードピン
埋込は簡素化されまたサーデイツプ形に比し多ピ
ン構成とすることができる大きな効果がある。 A semiconductor element 29 is mounted on a preform 25 on a ceramic substrate 28 as shown in the figure, and the preform 2
Heat fusion fixation is performed using a glass member having a lower melting point than No. 5. This is a consideration so as not to affect the adhesive strength of the external leads 23 that were previously fused. Thereafter, the signal line connection pad of the semiconductor element 29 and the tip 22b of the inner pattern 22 (see FIGS. 2 and 3) are bonded together using a wire 30, and the cap is sealed with glass using a ceramic cap 31 having a concave shape on the inside. Then, the connection part 21a connecting the frame 21 and the pattern 22 shown in FIG.
Surface treatment with solder dip etc. A semiconductor device constructed in this manner has the great effect that the ceramic substrate formation and lead pin embedding are simplified compared to the conventional pin grid array type, and it can be configured with a large number of pins compared to the cer-dip type.
(g) 発明の効果
以上詳細に説明したように本発明のピングリツ
ドアレイ構造とすることによりセラミツク基板の
メタライズパターン形成、チツプ搭載面の表面処
理は不要となり外部リード埋込処理は簡素化され
る。しかもガラス封止が可能となる等経済的で量
産化が可能となる大きな効果がある。(g) Effects of the Invention As explained in detail above, the pin grid array structure of the present invention eliminates the need for metallization pattern formation on the ceramic substrate and surface treatment of the chip mounting surface, simplifying the external lead embedding process. Ru. Moreover, it has great effects such as being able to be sealed with glass, making it economical and enabling mass production.
第１図は従来のピングリツドアレイ形半導体装
置を示す断面図、第２図は従来のサーデイツプ形
半導体装置を示す断面図、第３図は本発明の一実
施例であるインナーパターンを自す平面図、第４
図はインナーパターンに外部リードを取付けた断
面図、第５図のイ，ロ図は本発明の一実施例であ
るセラミツク基板を示す構成図でありイ図は構成
を説明するための分解図、ロは組立断面図、第６
図は本発明の一実施例であるピングリツドアレイ
形半導体装置を示す断面図である。
図中、２１はフレーム、２２はインナーパター
ン、２３は外部リード、２４，２６は貫通孔、２
５はプレフオーム、２７はセラミツクベース、２
８はセラミツク基板、２９は半導体素子、３０は
ワイヤ、３１はセラミツクキヤツプを示す。
FIG. 1 is a sectional view showing a conventional pin grid array type semiconductor device, FIG. 2 is a sectional view showing a conventional third dip type semiconductor device, and FIG. 3 shows an inner pattern according to an embodiment of the present invention. Floor plan, 4th
The figure is a cross-sectional view of the outer lead attached to the inner pattern, Figures A and B in Figure 5 are configuration diagrams showing a ceramic substrate that is an embodiment of the present invention, and Figure A is an exploded view for explaining the configuration. B is an assembled sectional view, No. 6
The figure is a sectional view showing a pin grid array type semiconductor device which is an embodiment of the present invention. In the figure, 21 is a frame, 22 is an inner pattern, 23 is an external lead, 24 and 26 are through holes, 2
5 is preform, 27 is ceramic base, 2
8 is a ceramic substrate, 29 is a semiconductor element, 30 is a wire, and 31 is a ceramic cap.
Claims (1)
び蓋板と、該基板上にガラス層を介して配置され
た金属板を打ち抜いて形成したリードフレームか
らなる内部配線と、該基板上に固着した半導体チ
ツプとを有し、該内部配線の両端はそれぞれ該半
導体チツプおよび該基板に埋め込まれたピンに電
気的に接続され、該基板と該蓋板はガラス層で融
着して封止されていることを特徴とする半導体装
置。1 A substrate and a lid plate of a pin grid array type package, internal wiring made of a lead frame formed by punching out a metal plate placed on the substrate through a glass layer, and a semiconductor chip fixed on the substrate. , both ends of the internal wiring are electrically connected to the semiconductor chip and the pins embedded in the substrate, respectively, and the substrate and the cover plate are fused and sealed with a glass layer. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168932A JPS5958851A (en) | 1982-09-28 | 1982-09-28 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168932A JPS5958851A (en) | 1982-09-28 | 1982-09-28 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5958851A JPS5958851A (en) | 1984-04-04 |
| JPS638620B2 true JPS638620B2 (en) | 1988-02-23 |
Family
ID=15877214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57168932A Granted JPS5958851A (en) | 1982-09-28 | 1982-09-28 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958851A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4890152A (en) * | 1986-02-14 | 1989-12-26 | Matsushita Electric Works, Ltd. | Plastic molded chip carrier package and method of fabricating the same |
| JPS6437842A (en) * | 1987-08-03 | 1989-02-08 | Shinko Electric Ind Co | Package for pga type semiconductor device |
| JPH01117084A (en) * | 1987-10-29 | 1989-05-09 | Nec Corp | Plastic pin grid array package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126951A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Semicondutor device |
| JPS56137645A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
| JPS5759454B2 (en) * | 1976-09-15 | 1982-12-15 | Tokico Ltd |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618608Y2 (en) * | 1980-09-26 | 1986-03-17 |
-
1982
- 1982-09-28 JP JP57168932A patent/JPS5958851A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5759454B2 (en) * | 1976-09-15 | 1982-12-15 | Tokico Ltd | |
| JPS56126951A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Semicondutor device |
| JPS56137645A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5958851A (en) | 1984-04-04 |
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