JPH0812896B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0812896B2 JPH0812896B2 JP60083836A JP8383685A JPH0812896B2 JP H0812896 B2 JPH0812896 B2 JP H0812896B2 JP 60083836 A JP60083836 A JP 60083836A JP 8383685 A JP8383685 A JP 8383685A JP H0812896 B2 JPH0812896 B2 JP H0812896B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- leads
- resin
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 229920001721 polyimide Polymers 0.000 claims description 17
- 239000004642 Polyimide Substances 0.000 claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 239000010949 copper Substances 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000037237 body shape Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はポリイミド系フィルム上にインナーリードと
アウターリードが一体化形成されたリードフレームに半
導体デバイスが搭載された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor device is mounted on a lead frame in which inner leads and outer leads are integrally formed on a polyimide film.
従来の技術 従来の半導体装置搭載用リードフレームは、Fe−Ni−
Co合金、Fe−Ni合金、Cu系合金を、その材料としてい
た。しかし、最近では、半導体デバイスを搭載したパッ
ケージの高密度実装が要求されるなかで、材料の改善は
おこなわれずに、寸法の縮小化に力点のおかれたパッケ
ージ設計に努力が注がれてきていた。従って寸法の小型
化は、必然的に金属性リードフレームの薄型指向へとつ
ながり、その結果として半導体デバイスを搭載したパッ
ケージのアウターリードの折り曲げ強度の低下や、アウ
ターリードフォーミング後のリード変形が起こってい
た。Conventional technology Conventional lead frames for mounting semiconductor devices are made of Fe-Ni-
Co alloy, Fe-Ni alloy, and Cu alloy were used as the material. However, recently, with the demand for high-density packaging of semiconductor device-mounted packages, efforts have been focused on package design with an emphasis on reducing dimensions without improving materials. It was Therefore, downsizing of dimensions inevitably leads to thinness of the metallic lead frame, and as a result, bending strength of the outer leads of the package in which the semiconductor device is mounted is reduced and lead deformation after outer lead forming occurs. It was
発明が解決しようとする問題点 リードフレームの材料がFe−Ni−Co合金やFe−Ni合
金、Cu系合金の場合、半導体デバイスを封止するモール
ド材（エポキシ系樹脂）との熱膨張係数が、Fe−Ni合金
で、4.4ppm/℃、樹脂で25ppm/℃と、大きく異なるため
に熱衝撃や温度サイクル等の環境試験で、樹脂とリード
フレームの境界面が剥離を生じ、この種の樹脂と金属の
組合わせにおいて、高湿の雰囲気での使用は、半導体デ
バイスの不良を誘発する主原因となっていた。Problems to be Solved by the Invention When the material of the lead frame is Fe-Ni-Co alloy, Fe-Ni alloy, or Cu-based alloy, the coefficient of thermal expansion with the molding material (epoxy-based resin) that seals the semiconductor device is , Fe-Ni alloy is 4.4ppm / ℃, and resin is 25ppm / ℃, which is very different from each other.Therefore, the interface between resin and lead frame peels off in the environmental test such as thermal shock and temperature cycle. In the combination of metal and metal, use in a high-humidity atmosphere has been a main cause of defective semiconductor devices.
また、樹脂封入の際、細線ワイヤー長が長いとワイヤ
ー形状が変形し、半導体デバイスや、隣接するワイヤー
同士が接触するという問題があった。In addition, when the resin is sealed, if the fine wire length is long, the wire shape is deformed, and there is a problem that the semiconductor device or adjacent wires come into contact with each other.
本発明は、従来例に見られた上述の問題点を一挙に解
決すると共に、広範囲の樹脂との組合わせを可能にする
ものである。The present invention solves the above-mentioned problems found in the conventional example all at once, and enables combination with a wide range of resins.
問題点を解決するための手段 本発明は要約すると、ポリイミド系フィルム上に、C
u,Cu系合金または有機導電性材料によりインナーリー
ド、アウターリードおよび配線パターンを施したリード
フレームを準備し、そこに半導体デバイスを装着して樹
脂封止を行い、さらにインナーリードとアウターリード
との一部をポリイミド系テープで覆い、かつ、アウター
リードを覆うポリイミドテープの少なくともリード間の
箇所に、はんだ逃げ孔を設けた半導体装置である。Means for Solving Problems The present invention is summarized as follows.
Prepare a lead frame with inner leads, outer leads, and wiring patterns made of u, Cu-based alloy or organic conductive material, mount a semiconductor device on it and perform resin encapsulation. This is a semiconductor device in which a polyimide tape is partially covered, and a solder escape hole is provided at least at a position between the leads of the polyimide tape that covers the outer leads.
作用 ポリイミドテープまたはポリイミドシート上に薄い金
属あるいは導電材料が電極リードとして形成されたリー
ドフレームを用いるために、これに半導体デバイスを樹
脂封止した場合の樹脂封止特性がよく、耐熱性にもすぐ
れる。Action Since a lead frame in which a thin metal or conductive material is formed as an electrode lead on a polyimide tape or polyimide sheet is used, the resin encapsulation characteristics when the semiconductor device is encapsuled with resin are good, and the heat resistance is also fast. Be done.
実施例 次に、本発明を実施例により詳しく述べる。EXAMPLES Next, the present invention will be described in detail with reference to Examples.
第１図は、本発明の実施例の半導体装置を示した全体
外観斜視図である。リードフレーム１は、耐熱性（300
℃以上）を有し、熱膨張係数が約30〜40ppm/℃で厚さ0.
05〜0.5mmのポリイミド系テープ２と、電気的導通を図
るために熱膨張係数が約17ppm/℃で厚さ0.03〜0.25mmの
CuまたはCu系合金からなる配線パターンのリード３で形
成されている。これにトランスファーモールドで熱膨張
係数が約25ppm/℃のエポキシ系樹脂４により形成する。
なお、エポキシ封止樹脂４が装着される前のリードフレ
ーム１は図示しないが、リード３を構成するインナーリ
ードとアウターリードとがリードフレーム１と一体化形
成されている。インナーリードはエポキシ系樹脂４で封
止されたリード３の部分であり、アウターリードはエポ
キシ系樹脂４の外側の部分を指す。したがって、第１図
に符号３で示されたリードの箇所はアウターリードの部
分を示し、かつ、アウターリード（リード３）が折り曲
げられた状態を示している。FIG. 1 is an overall external perspective view showing a semiconductor device according to an embodiment of the present invention. Lead frame 1 is heat resistant (300
℃ or more), the coefficient of thermal expansion is about 30-40ppm / ℃ and the thickness is 0.
05-0.5mm polyimide tape 2 with a thermal expansion coefficient of about 17ppm / ℃ and a thickness of 0.03-0.25mm for electrical conduction.
It is formed of leads 3 of a wiring pattern made of Cu or a Cu-based alloy. The epoxy resin 4 having a thermal expansion coefficient of about 25 ppm / ° C. is formed thereon by transfer molding.
The lead frame 1 before the epoxy sealing resin 4 is mounted is not shown, but inner leads and outer leads forming the leads 3 are integrally formed with the lead frame 1. The inner lead is a portion of the lead 3 sealed with the epoxy resin 4, and the outer lead is a portion outside the epoxy resin 4. Therefore, the portion of the lead shown by reference numeral 3 in FIG. 1 shows the outer lead portion and also shows the state in which the outer lead (lead 3) is bent.
エポキシ系封止樹脂４の内部は、第１図のＡ−Ａ線に
沿った第２図の断面図に示すように、インナーリード先
端部５がバンプ付き構造をなしており、さらにその表面
は、0.5〜5.0μｍの厚みのAuメッキか、無酸化銅の塊に
なっている。このインナーリード先端部５が半導体デバ
イス７上のAlボンディングパッド６に熱圧着または、サ
ーモソニック法で接続されている。これらリードフレー
ム１はトランスファーモールド法で樹脂成形を行うため
に、第３図に示す封止連体形状図のように、所要の寸法
に切断される。しかし、一貫自動化ラインでは、定尺に
切断する必要はない。As shown in the sectional view of FIG. 2 taken along the line AA of FIG. 1, the inside of the epoxy encapsulating resin 4 has a structure in which the inner lead tips 5 have bumps, and the surface thereof is , 0.5-5.0 μm thick Au plating or non-oxidized copper lumps. The inner lead tip portion 5 is connected to the Al bonding pad 6 on the semiconductor device 7 by thermocompression bonding or thermosonic method. Since these lead frames 1 are resin-molded by the transfer molding method, they are cut into required dimensions as shown in the shape of the sealing body shown in FIG. However, it is not necessary to cut to a fixed length in the integrated automation line.
さらにテスティングは、テープ状のままか、リード３
とポリイミド系テープ２が一体のままで、リードフォー
ミング後に行う。Furthermore, the testing can be done in the form of tape or lead 3
After the lead forming, the polyimide tape 2 and the polyimide tape 2 are integrated.
組立工程における送り方法は、ポリイミド系テープの
両端に設けられた送り孔８を用いて行い、裏側はリード
３と同じ金属材料で補強する。また、はんだ付けに適合
できるように、リードフレーム１基体のポリイミド系テ
ープ２の一部に、はんだ逃げ孔９をスリット状に設けて
おくとよい。The feeding method in the assembling process is performed by using the feeding holes 8 provided at both ends of the polyimide tape, and the back side is reinforced with the same metal material as the leads 3. Further, in order to be suitable for soldering, it is preferable to form a solder escape hole 9 in a slit shape in a part of the polyimide tape 2 of the lead frame 1 base.
発明の効果 本発明はポリイミド系のリードフレームにその熱膨張
係数と近いCuの導電層を形成し、さらにそのリードフレ
ームを熱膨張係数に近いエポキシ系樹脂で封止するの
で、温度変化に対しての信頼性が低下しない。また、Cu
系のリードをラミネートしたポリイミド系テープを用い
ているので、薄型小型パッケージ等で問題になってい
る。リード断線やリード変形が皆無になる。また、半導
体デバイスとリードの接続には、ワイヤーではなくバン
プにより行っているため、封止の際のワイヤー同士が接
触するということはなくなる。なお、アウターリード
は、リード箔とポリイミドテープを薄型化すれば、フレ
キシビリティーの高いアウターリードが実現でき、逆に
両者に厚い材料を用いれば、現状見られるような、機械
的に強固なアウターリードが実現できる。EFFECTS OF THE INVENTION The present invention forms a Cu conductive layer having a thermal expansion coefficient close to that of a polyimide-based lead frame, and further seals the lead frame with an epoxy resin having a thermal expansion coefficient close to that of a temperature change. Does not reduce the reliability of. Also, Cu
Since a polyimide tape laminated with system leads is used, it is a problem in thin and small packages. No lead wire breakage or lead deformation. Further, since the semiconductor device and the lead are connected not by the wire but by the bump, the wires do not come into contact with each other at the time of sealing. The outer leads can be made highly flexible by thinning the lead foil and the polyimide tape, and conversely, if thick materials are used for both, the mechanically strong outer leads can be seen. Lead can be realized.
第１図、第２図、第３図はそれぞれ本発明の半導体装置
の実施例の外観斜視図、要部断面図、封止連体形状図で
ある。 １……リードフレーム、２……ポリイミド系テープ、３
……CuまたはCu系合金リード、４……エポキシ系封止樹
脂、５……インナーリード先端部、６……Alボンディン
グパッド、７……半導体デバイス、８……送り孔、９…
…はんだ逃げ孔。FIG. 1, FIG. 2 and FIG. 3 are an external perspective view, a sectional view of a main part, and a sealing body shape diagram of an embodiment of a semiconductor device of the present invention, respectively. 1 ... Lead frame, 2 ... Polyimide tape, 3
...... Cu or Cu alloy lead, 4 epoxy resin, 5 inner lead tip, 6 Al bonding pad, 7 semiconductor device, 8 feed hole, 9
… Solder escape holes.
Claims (1)
スを接続するためのインナーリードとこれに連なるアウ
ターリードおよび、Cu,Cu系合金または有機導電性材料
により形成された配線パターンが一体化形成されたリー
ドフレームと、前記リードフレームに装着された半導体
デバイスと、前記インナーリードおよびアウターリード
の一部を覆うポリイミド系テープと、前記半導体デバイ
スおよびインナーリードが樹脂封止されたパッケージ
と、少なくとも前記アウターリードを覆う前記ポリイミ
ド系テープのアウターリード間に、はんだ逃げ孔を設け
たことを特徴とする半導体装置。1. An inner lead for connecting a semiconductor device, an outer lead connected to the inner lead, and a wiring pattern formed of Cu, a Cu-based alloy or an organic conductive material are integrally formed on a polyimide film. A lead frame, a semiconductor device mounted on the lead frame, a polyimide tape covering a part of the inner lead and the outer lead, a package in which the semiconductor device and the inner lead are resin-sealed, and at least the outer lead. A semiconductor device characterized in that a solder escape hole is provided between the outer leads of the polyimide tape covering the cover.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083836A JPH0812896B2 (en) | 1985-04-19 | 1985-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083836A JPH0812896B2 (en) | 1985-04-19 | 1985-04-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61242051A JPS61242051A (en) | 1986-10-28 |
| JPH0812896B2 true JPH0812896B2 (en) | 1996-02-07 |
Family
ID=13813785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60083836A Expired - Lifetime JPH0812896B2 (en) | 1985-04-19 | 1985-04-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812896B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63260058A (en) * | 1987-04-16 | 1988-10-27 | Nec Corp | Manufacture of semiconductor device |
| US4796078A (en) * | 1987-06-15 | 1989-01-03 | International Business Machines Corporation | Peripheral/area wire bonding technique |
| JPH02260447A (en) * | 1989-03-30 | 1990-10-23 | Matsushita Electric Ind Co Ltd | Ic package |
| JPH02260445A (en) * | 1989-03-30 | 1990-10-23 | Matsushita Electric Ind Co Ltd | Ic package |
| JP5169185B2 (en) * | 2007-12-05 | 2013-03-27 | 日亜化学工業株式会社 | Light emitting device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134045A (en) * | 1984-12-05 | 1986-06-21 | Nec Corp | Resin-sealed semiconductor device |
-
1985
- 1985-04-19 JP JP60083836A patent/JPH0812896B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61242051A (en) | 1986-10-28 |
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