JPS6341205B2 - - Google Patents
Info
- Publication number
- JPS6341205B2 JPS6341205B2 JP55067736A JP6773680A JPS6341205B2 JP S6341205 B2 JPS6341205 B2 JP S6341205B2 JP 55067736 A JP55067736 A JP 55067736A JP 6773680 A JP6773680 A JP 6773680A JP S6341205 B2 JPS6341205 B2 JP S6341205B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- dielectric
- layers
- layer
- composite component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
本発明は、複数のコンデンサを内蔵した基板形
式の積層複合部品に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a laminated composite component in the form of a substrate containing a plurality of capacitors.
誘電体層と電極層とを交互に多数積層し、積層
体の側辺に外部端子を被着して成る積層チツプコ
ンデンサは知られている。しかし、積層チツプコ
ンデンサはあくまで電子回路の単位素子を構成す
るに過ぎない。 A multilayer chip capacitor is known in which a large number of dielectric layers and electrode layers are alternately stacked and external terminals are attached to the sides of the stack. However, multilayer chip capacitors merely constitute unit elements of electronic circuits.
本発明は誘電体層を各種電子素子(抵抗体、コ
イル、ダイオード、トランジスタ等)が塔載でき
るに十分な面積にし、複数の電極層を並列的に誘
電体層と交互積層する。さらに誘電体層を2種以
上の異つた材質の誘電体から構成し、このため、
容量値の非常に異つた多数のコンデンサを一体的
に内蔵した複合部品とする。従つて、本発明の複
合部品はこれらのコンデンサを任意に選択結線し
て任意の容量値を得ることができるだけでなく、
本複合部品の表裏面にプリント配線を施してプリ
ント基板としても使用できる。好ましい実施例で
は本発明の複合部品の表裏にはプリント配線と抵
抗体とを印刷しておくことができる。これにより
トランジスタ等を半田づけするだけで必要な回路
を構成することができる。本発明の中心的な特徴
は異つた材質の誘電体層が使用されること、各材
質の誘電体に対して複数の並列コンデンサが形成
されていること、そして積層体の表面が各種部品
用の基板となりうることである。 In the present invention, the dielectric layer has a sufficient area to mount various electronic elements (resistors, coils, diodes, transistors, etc.), and a plurality of electrode layers are alternately laminated with the dielectric layer in parallel. Furthermore, the dielectric layer is composed of dielectrics made of two or more different materials, and therefore,
It is a composite component that integrates a large number of capacitors with very different capacitance values. Therefore, the composite component of the present invention not only allows these capacitors to be connected arbitrarily to obtain an arbitrary capacitance value, but also
This composite part can also be used as a printed circuit board by applying printed wiring to the front and back sides. In a preferred embodiment, printed wiring and resistors can be printed on both sides of the composite component of the present invention. This allows the necessary circuit to be constructed simply by soldering transistors and the like. The central features of the invention are that dielectric layers of different materials are used, that a plurality of parallel capacitors are formed for each dielectric material, and that the surface of the laminate is used for various components. It can be used as a substrate.
以下図面に関連して本発明の実施例を詳しく説
明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図ないし第5図は積層複合部品の各層の平
面図を示す。第1図に示すように本部品は絶縁体
または誘電体層1の上に複数のAl−Pd又はPd等
の電極層2,3,4,5,6を印刷等により形成
した構成部分を有する。電極層2ないし6は上端
を引出部T1ないしT5として誘電体層1の上辺に
露出している。なお、この電極層2,3,4,
5,6はそれぞれ所望の容量値を得るため、電極
面積をそれぞれ所定の大きさに構成している。第
1図に示した層の上には第2図の構成部分が積層
されている。誘電体層1の全面を覆つてたとえば
BaTiO3などの高誘電率を有する誘電体層7が形
成され、その面に今度は積層体の下辺に露出する
引出部T1′ないしT5′を有する電極層2′ないし
6′が下側の電極層2ないし6にそれぞれ対向す
るように形成されている。第2図の構成部分の上
には熱膨脹係数が異種誘電体層間で違うことによ
る熱収縮歪、反り又は割れが生じるのを防止する
ため、第3図のように誘電体層7と後記の誘電体
層13との中間的な熱膨脹係数を有する誘電体層
8(例えばTiO2とBaTiO3の混合焼成体)が全面
に形成され、さらに引出部T1ないしT5の間に引
出部T6ないしT9を有する電極層9ないし12が
形成される。さらにこの上に第4図に示すように
例えばTiO2より成る低誘電率を有する誘電体層
13が全面に形成される。誘電体層13の材質は
誘電体層7の材質とは異つたものである。これは
電極層の寸法がほとんど差がなくても容量値が大
きく変つた多数のコンデンサを用意するためであ
る。誘電体層13の上面には下側の電極層9ない
し12にそれぞれ対向する電極層9′ないし1
2′を印刷等で形成されている。T6′ないしT9′は
電極層9′ないし12′の引出部で、第2図に示し
た引出部T1′ないしT5′の間に設けられる。最後に
第5図Aのように誘電層14が積層体の全面に被
覆されている。第5図Aは本発明による積層複合
部品の完成品を示す外観図である。第5図Bは第
5図AのA−A′断面図を示す。 1 to 5 show plan views of each layer of the laminated composite part. As shown in Figure 1, this component has a component in which a plurality of electrode layers 2, 3, 4, 5, 6 made of Al-Pd or Pd are formed on an insulator or dielectric layer 1 by printing, etc. . The upper ends of the electrode layers 2 to 6 are exposed on the upper side of the dielectric layer 1 as lead-out portions T 1 to T 5 . Note that these electrode layers 2, 3, 4,
In order to obtain desired capacitance values, electrode areas 5 and 6 are each configured to have a predetermined size. The components shown in FIG. 2 are laminated on top of the layers shown in FIG. For example, by covering the entire surface of the dielectric layer 1,
A dielectric layer 7 having a high dielectric constant such as BaTiO 3 is formed, and electrode layers 2' to 6' having lead-out portions T1 ' to T5 ' exposed at the lower side of the laminate are formed on the lower side. are formed to face the electrode layers 2 to 6, respectively. In order to prevent thermal shrinkage distortion, warping, or cracking due to differences in thermal expansion coefficients between dielectric layers of different types, a dielectric layer 7 and a dielectric layer 7 as shown in FIG. A dielectric layer 8 (for example, a mixed sintered body of TiO 2 and BaTiO 3 ) having a thermal expansion coefficient intermediate to that of the body layer 13 is formed on the entire surface, and further there are drawn parts T 6 to T 5 between the drawn parts T 1 to T 5 . Electrode layers 9 to 12 with T 9 are formed. Furthermore, as shown in FIG. 4, a dielectric layer 13 made of, for example, TiO 2 and having a low dielectric constant is formed over the entire surface. The material of the dielectric layer 13 is different from the material of the dielectric layer 7. This is to prepare a large number of capacitors whose capacitance values vary greatly even if the dimensions of the electrode layers are almost the same. On the upper surface of the dielectric layer 13, there are electrode layers 9' to 1 opposite to the lower electrode layers 9 to 12, respectively.
2' is formed by printing or the like. T 6 ′ to T 9 ′ are lead-out portions of the electrode layers 9′ to 12′, and are provided between the lead-out portions T 1 ′ to T 5 ′ shown in FIG. Finally, as shown in FIG. 5A, a dielectric layer 14 is applied over the entire surface of the stack. FIG. 5A is an external view showing a completed product of the laminated composite part according to the present invention. FIG. 5B shows a sectional view taken along line AA' in FIG. 5A.
以上の積層構造は本発明に特有であるが、その
製造方法は従来公知の積層チツプコンデンサと同
様な方法を採用すれば良い。例えば各層を第1図
から第5図の順に各原料粉末のペーストを印刷し
て積層し、高温で焼成して一体化した焼結体とす
れば良い。最後に、第5図のように積層体の側辺
に露出している引出部T1ないしT9、及びT1′ない
しT9′に外部端子(同じ符号で示す)が焼付けら
れており、さらに必要に応じて接続端子T10,
T11,T12が焼付けられている。なお電極層1な
いし12及び1′ないし12′は設計目的に応じて
種々の面積を有するように選択されている。 Although the above laminated structure is unique to the present invention, the manufacturing method thereof may be the same as that for conventionally known laminated chip capacitors. For example, each layer may be laminated by printing a paste of each raw material powder in the order shown in FIGS. 1 to 5, and then fired at a high temperature to form an integrated sintered body. Finally, as shown in FIG. 5, external terminals (indicated by the same reference numerals) are baked into the lead-out portions T 1 to T 9 and T 1 ′ to T 9 ′ exposed on the sides of the laminate. In addition, if necessary, connect terminal T 10 ,
T 11 and T 12 are baked. Note that the electrode layers 1 to 12 and 1' to 12' are selected to have various areas depending on the design purpose.
第6図は本発明の積層複合部品の応用を示す斜
視図である。図中20は第1〜2図に、30は第
3〜5図に相当する。第1〜5図のように構成さ
れた複合部品の表裏面はスペースがある平面であ
り、そこに必要に応じてプリント配線15を施
す。なお、この実施例ではさらに酸化ルテニウム
等の抵抗体R1,R2,R3,R4が印刷、焼付され
る。なお、この表裏面には、抵抗体ばかりでな
く、インダクタンス素子、トランストランジス
タ、ダイオード等を配置し、固定することもでき
る。さらに外部端子T1,T2等も回路設計に応じ
て相互接続することもできる。図のT1′,T6′がそ
の1例である。 FIG. 6 is a perspective view showing an application of the laminated composite part of the present invention. In the figure, 20 corresponds to FIGS. 1-2, and 30 corresponds to FIGS. 3-5. The front and back surfaces of the composite component configured as shown in FIGS. 1 to 5 are planes with spaces, and printed wiring 15 is applied thereto as necessary. In this embodiment, resistors R 1 , R 2 , R 3 , and R 4 made of ruthenium oxide or the like are further printed and baked. Note that not only resistors but also inductance elements, transformer transistors, diodes, etc. can be arranged and fixed on the front and back surfaces. Furthermore, external terminals T 1 , T 2 , etc. can also be interconnected depending on the circuit design. T 1 ′ and T 6 ′ in the figure are examples.
以上のように、本発明によると多数の各種の任
意の容量値のコンデンサを有する積層複合部品が
提供できる。例えば容量値として数十pFから数
千pFまでの広い範囲で異つたコンデンサを有す
る複合部品は異つた誘電体を組合わせて容易に構
成できる。そして複合部品の表裏を用いて抵抗等
を配置してプリント配線することができるから小
型の集積回路となる。しかも、辺部にすべての外
部端子が露出しているからプリント基板へこの複
合部品を塔載して半田づけする作業も容易であ
る。 As described above, according to the present invention, it is possible to provide a laminated composite component having a large number of various capacitors with arbitrary capacitance values. For example, a composite component having capacitors with different capacitance values in a wide range from several tens of pF to several thousand pF can be easily constructed by combining different dielectric materials. Since resistors and the like can be placed and printed wiring using the front and back sides of the composite component, a compact integrated circuit can be obtained. Moreover, since all external terminals are exposed on the sides, it is easy to mount and solder this composite component onto a printed circuit board.
なお実施例は2種の誘電体を用い、しかも各層
は単一層から成るものとして説明したが、3種以
上の誘電体を用いても良く、また各コンデンサは
複数層の誘電体と電極層との交互積層体として構
成することもできる。 Although the embodiment has been described using two types of dielectrics and each layer consisting of a single layer, three or more types of dielectrics may be used, and each capacitor may include multiple layers of dielectrics and electrode layers. It can also be constructed as an alternating laminate of.
第1図は本発明の複合部品の最下層部分の平面
図、第2図は第2部分の平面図、第3図は第3部
分の平面図、第4図は第4部分の平面図、第5図
Aは最上層部分の平面図を示す。第5図BはAの
A−A′断面図である。第6図は本発明の複合部
品の斜視図で、表面に抵抗及びプリント配線が施
された図である。図中主な部分は次の通り。
1:最下層誘電体層、7:第1の材質の誘電体
層、8:中間層誘電体層、13:第2の材質の誘
電体層、14:最上層誘電体層、2,3,4,
5,6:電極層(第1組)、2′,3′,4′,5′,
6′:電極層(第2組)、9,10,11,12:
電極層(第3組)、9′,10′,11′,12′:
電極層(第4組)。
FIG. 1 is a plan view of the lowest layer of the composite component of the present invention, FIG. 2 is a plan view of the second portion, FIG. 3 is a plan view of the third portion, and FIG. 4 is a plan view of the fourth portion. FIG. 5A shows a plan view of the top layer portion. FIG. 5B is a sectional view taken along line A-A' of A. FIG. 6 is a perspective view of a composite component of the present invention, with resistors and printed wiring provided on the surface. The main parts in the diagram are as follows. 1: Bottom dielectric layer, 7: Dielectric layer made of first material, 8: Intermediate dielectric layer, 13: Dielectric layer made of second material, 14: Top dielectric layer, 2, 3, 4,
5, 6: electrode layer (first set), 2', 3', 4', 5',
6': Electrode layer (second set), 9, 10, 11, 12:
Electrode layer (third set), 9', 10', 11', 12':
Electrode layer (4th set).
Claims (1)
十分な面積を有する誘電体層と容量形成用の電極
層との相互積層体より成る複合部品において、前
記積層体は、第1の誘電率を有する誘電体層と複
数の電極層との交互積層体より成る第1の並列コ
ンデンサ部、前記第1のコンデンサ部の誘電体層
とは誘電率の異なつた第2の誘電体層と複数の電
極層との交互積層体より成る第2の並列コンデン
サ部、および前記第1および第2の並列コンデン
サ部のうち隣り合つた誘電体層の間に設けられ、
これら誘電体層の中間の熱膨張係数を有する誘電
体層、を基本構成とする一体焼結体より構成され
ていることを特徴とする複合部品。1. In a composite component consisting of a mutually laminated body of a dielectric layer and an electrode layer for forming a capacitor, each having a surface area sufficient to mount various electronic elements on the surface of the laminated body, the laminated body has a first dielectric constant. a first parallel capacitor section consisting of an alternating stack of dielectric layers and a plurality of electrode layers; a second dielectric layer having a dielectric constant different from that of the dielectric layer of the first capacitor section; a second parallel capacitor section made of an alternating laminate with electrode layers; and a second parallel capacitor section provided between adjacent dielectric layers of the first and second parallel capacitor sections;
A composite component characterized in that it is constituted by an integral sintered body whose basic structure is a dielectric layer having a thermal expansion coefficient between those of these dielectric layers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6773680A JPS56164516A (en) | 1980-05-23 | 1980-05-23 | Composite part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6773680A JPS56164516A (en) | 1980-05-23 | 1980-05-23 | Composite part |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56164516A JPS56164516A (en) | 1981-12-17 |
JPS6341205B2 true JPS6341205B2 (en) | 1988-08-16 |
Family
ID=13353532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6773680A Granted JPS56164516A (en) | 1980-05-23 | 1980-05-23 | Composite part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56164516A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0553519U (en) * | 1991-12-27 | 1993-07-20 | 株式会社サカン | Grip belt |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6035568U (en) * | 1983-08-18 | 1985-03-11 | ティーディーケイ株式会社 | hybrid integrated circuit |
JPS61196517U (en) * | 1985-05-28 | 1986-12-08 | ||
JPH02142109A (en) * | 1988-11-23 | 1990-05-31 | Tdk Corp | Integrated circuit component |
JPH11126730A (en) * | 1997-10-24 | 1999-05-11 | Matsushita Electric Ind Co Ltd | Manufacturing method of multiple electronic components |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54138206A (en) * | 1978-04-19 | 1979-10-26 | Mitsubishi Electric Corp | On-train trouble informaiton processing system |
-
1980
- 1980-05-23 JP JP6773680A patent/JPS56164516A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0553519U (en) * | 1991-12-27 | 1993-07-20 | 株式会社サカン | Grip belt |
Also Published As
Publication number | Publication date |
---|---|
JPS56164516A (en) | 1981-12-17 |
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