JPS63312715A - Delay circuit - Google Patents

Abstract

PURPOSE:To make the delay time of a delaying circuit constant without being influenced by the fluctuation of a power source voltage, temperature, etc., by comparing the potential of the node connecting a capacity and a resistance with a referring potential with a voltage comparator, and outputting a size relation. CONSTITUTION:A capacity C1 executes the discharging and charging in accordance with the input of an input signal the inverse of phi. A potential V2 at a connection node of the capacity C1 and an R1 connected to this, a referring voltage V1 obtained by voltage-dividing a power source voltage VCC with resistances R3 and R4 are compared by a voltage comparator 10, and an output phi2 is outputted based on the size relation. In such a case, since the time tauwhen the output phi2 is transferred from a low level to a high level, is specified by the capacity C1 and resistances R1, R3 and R4, the time is not influenced by the characteristic of the power source and MOS transistors 11 and 12.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a delay circuit used in an integrated circuit (prior art) In a DRAM or other semiconductor integrated circuit, a plurality of circuits are synchronized. Various delay circuits are used to set the timing when the device operates on a regular basis.

When a CMOS process is used, the delay circuit can be constructed by connecting inverters in multiple stages as shown in FIG. In this circuit, the number of inverter stages, the inverter ratio (
By adjusting the dimensions of the transistors constituting the inverter (funout), an arbitrary delay time (τ; the time from the input of φ1 to the output of φ2) can be obtained.

However, this type of delay circuit has the following problems. In general, delay circuits are required to be insensitive to changes in power supply voltage, temperature changes, process parameter changes, etc., and always have constant delay characteristics. In contrast, in inverter-type delay circuits that have been proposed in the past, for example, the delay time becomes shorter as the power supply voltage rises, the delay time becomes longer as the temperature rises, and the process parameters (
■yh e Iim + Tox e C1e) The delay time is sensitively affected by fluctuations, etc., making it difficult to achieve desired characteristics.

(Problems to be Solved by the Invention) As described above, the delay circuits proposed in the past are sensitive to fluctuations in power supply voltage, temperature, process parameters, etc., and ensure the desired delay time. was difficult to obtain.

The present invention has been made in view of the above points, and an object of the present invention is to provide a delay circuit that is insensitive to fluctuations in power supply voltage, temperature, process parameters, etc. and can always obtain a constant delay time.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a method for charging (discharging) the capacitor CI via the resistor R1 and connecting the capacitor CI to a reference potential node obtained by dividing the power supply voltage or via a resistor island. The present invention is characterized by providing means for starting discharging (charging) and discharging (charging) at the same time, detecting that the potentials of both are reversed, and outputting the time.

(Function) According to the present invention, it is possible to realize a delay circuit in which the delay time is determined only by CB and the time constant, that is, it is not affected by fluctuations in power supply voltage or variations in characteristics of MOS transistors. In general, in the integrated circuit process, resistors made from diffusion layers, polycrystalline Si, etc., and capacitors made from MOS and PN junctions can be relatively easily formed into elements with desired values. Moreover, the temperature dependence of these values is extremely small. Therefore, a circuit with a constant delay time can be easily obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a delay circuit according to an embodiment.

In the figure, 10 is a comparator, and its + side Vs (
1)=Enter. (1-e-4 pieces) ・・・・・・・・・ (
2). Here, the output φ8 is “L”
The time τ at which “H”K transitions from node 13 to node 14
Since this is when the potential relationship of is reversed, Vm(τ)=V,
Considering (11, (from formula 21, voC(1"1"I)="s%/(horse+"s)
−−(3) Therefore, τ=(” is horselog (]+horse/
R8)......obtained by (4). FIG. 2 shows an operation timing diagram of this embodiment. As is clear from equation (4), in the circuit of this embodiment, the power supply voltage V. 0 or M
A delay time that is completely unaffected by the characteristics of the OS transistor can be obtained.

Furthermore, in the MOS process, it is relatively easy to control the film thickness of the oxide film and the specific resistance of the wiring material, the capacitance is determined by the area of the polysilicon of the MOS capacitor, and the resistance is determined by the aspect ratio of the diffusion layer or polysilicon, etc. during mask design. By setting the geometric dimensions of , arbitrary C and R, that is, delay time τ can be obtained. Furthermore, changes in constants due to temperature changes are so small that they can be ignored in practical use.

In the above-mentioned example, the power supply voltage V is applied to the + side input terminal of the comparator. If a fixed potential divided from 0 is input, but the through current that constantly flows through the voltage dividing resistor becomes a problem,
A CR charging/discharging circuit that operates in a phase opposite to that on one side may be connected to this terminal. Furthermore, if the comparator is activated only when the delay circuit is operating, a delay circuit in which no through current flows during the timing can be obtained. One embodiment is shown in FIG. 3, and the operation timing is shown in FIG. 4.

In FIG. 3, MOS transistors 21 to 25 constitute a current mirror type differential amplifier and operate as a voltage comparator for nodes v1*vl.

This circuit sets the gate voltage φ and W of the transistor 21 to 1L.
When it is set to "H" level, it operates as a comparator, but when it is set to "H" level, it stops operating and reduces the through current.
Can be set to 0. Node v1 has birds, C,, M
OS) A CR charging/discharging circuit composed of transistors 28 and 29 is connected, and a CR charging and discharging circuit composed of R, C, and MOS transistors 26, 27, which operate in opposite phase to node v1, is connected to nodes v and 14. has been done.

When input j is at “H” level, C! is charged by the MOS transistor 26 with Vcct. Also CI
is completely discharged by the transistor 29 (MOS). At this time, the output 4 of the comparator is at "H# level."

Here, when 1=0 and the input φ transitions from "H" to "L#", the on-resistance of the MOS transistors 27 and 28 is as follows.
If the birds are small enough, nodes v1 and V! potential v1 of
(S, V!(t) are respectively vl(t)=voo(1
-e-I)・・・・・・・・・(5)vt(1=vo
, e-floor ・・・・・・・・・・・・・・・ +6
It is expressed as 1. Therefore, the output of the comparator φ. is “H”
The time τ at which the # level transitions from the “L” level is v, (τ)
= V, since it is a kantan from (τ), if C1 horse = C, R, :CR, then from equation (7), τ = CR, log2 ・・・・・・・・・・・・・・・
(8) becomes. Here, as in the embodiment shown in FIG. 1, by appropriately setting the value of the capacitance C1 resistance, the power supply voltage v
A delay circuit that is completely unaffected by the characteristics of transistors (OCS and MOS) can be obtained. Also, at 11 o'clock φ, W is set to “H”.
By adjusting the level, the through current can be reduced to 0.

FIG. 5 shows an embodiment of a circuit that automatically returns the converter to the start-up standby state recess after one hour has elapsed in the embodiment of FIG. 3 to cut off the through current. The operation timing is shown in FIG. In this circuit, for the input of φ,
, becomes the delayed signal. Further, 36 and 37 are simple delay circuits for preventing whiskers, and can be constructed from, for example, an inverter chain.

As described above, the delay circuit according to the embodiment can have an arbitrary delay time that is not affected by the power supply voltage, temperature, or characteristics of the MOS transistor, and can realize a circuit in which no through current flows during standby.

The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a delay circuit that is insensitive to fluctuations in power supply voltage, temperature, and process parameters, can set an arbitrary time, and does not allow a through current to flow during standby.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a delay circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing its operation time chart, and FIG. 3 is a diagram showing a specific configuration of another embodiment. FIG. 4 is a diagram showing its operation timing chart, FIG. 5 is a diagram showing a configuration example of the control circuit of the comparator, FIG. 6 is a diagram showing a timing chart explaining its operation, and FIG. 7 is a conventional delay circuit. FIG. 10... Comparator, 11, 26.28... P channel MO8) transistor (switching element), 12
．． 27.29...N-channel MOS transistor (switching element), φ1...Input signal, φ snow, φ snow・
...output signal, bird, 几3...divider resistance, 36.37.
...Delay circuit. Agent Patent Attorney Nori Ken Yudo Matsuyama Hikaru v'cc Figure 1 Figure 3 Figure A Figure 5 Figure 6 Figure 7

Claims (4)

[Claims] (1) A series circuit of a capacitor and a resistor that starts charging or discharging in response to an input signal, a circuit that generates a reference potential, and a comparison between the potential of the connection node of the capacitor and the resistor and the reference potential to determine the magnitude relationship between them. A delay circuit characterized by having a voltage comparator that outputs. (2) The delay circuit according to claim 1, wherein the reference potential is obtained by dividing the power supply voltage using resistors. (3) The delay according to claim 1, wherein the reference potential is provided from a connection node of a second series circuit of a capacitor and a resistor, which is charged and discharged in an opposite phase to the series circuit of a capacitor and a resistor. circuit. (4) The voltage comparator has a self-control function that cuts off the through current during standby, is activated by the input signal, and returns to the standby state again by the signal after outputting the delayed signal. Or the delay circuit described in item 3.