JPS63217820A - Cmos delay circuit - Google Patents

Abstract

PURPOSE:To decrease the power supply fluctuation or temperature fluctuation by inserting a resistor between a capacitive component and a drain of a transistor (TR) being a component of the 1st CMOS inverter including the capacitive component connected between a fixed potential point and a connecting point of 1st and 2nd CMOS inverters. CONSTITUTION:A resistor 18 comprising a diffusion layer or the like is connected in series with a drain of a P-channel MOS transistor (TR) of a CMOS inverter 12. The resistor 18 is used to retard the charging of a MOS capacitor 14. The drain of an N-channel MOS TR is connected to the drain of the P- channel MOS TR 16 via a resistor 18 to form a CMOS inverter. Thus, the effect of the power supply fluctuation of a delay circuit section is suppressed lower.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to CMOS circuits, and particularly to delay circuits.

[Conventional technology]

The delay circuit of the MO8 integrated circuit is generally constructed of delay elements such as MOS transistors and MOS capacitors to realize the timing required for circuit functions.

Figure 3 is a circuit diagram showing a conventional example of a delay circuit.
The output of CMOS inverter 12 with input is terminal 1
5 to the input of the next stage CMOS inverter 13, and the output of this CMOS inverter 13 is connected to the output terminal 4.
It is connected to the. A MOS capacitor 14 is connected between the terminal 15 and the low potential terminal 11.

is provided. The delay time of this circuit is determined by the channel width and channel length of the CMOS inverter 12, and the MO
Needless to say, it is determined by the load capacity of the S capacitor 14.

[Problem that the invention seeks to solve]

However, in the conventional delay circuit described above, the ON resistance of the MOS transistor constituting the CMOS inverter 12 that charges and discharges the load capacitance of the MOS capacitor 14 is directly affected by power fluctuations. The disadvantage is that the delay time is unstable.

The specific data is shown in FIG. 3(b). The horizontal axis represents the P channel and N channel constituting the CMOS inverter 12.
The vertical axis shows the channel length of the transistor (channel MOS), and the vertical axis shows the :M extension time between terminals 3 and 4, with VDD=4.5V and SV. It can be seen that in either case, the power supply voltage fluctuation directly affects the delay time.

In addition, in the same figure, a P-channel MO8) transistor and an N-channel MOS that constitute the CMOS inverter 12 are shown.
) The transistor channel widths are 48ttm and 78μ, respectively.
tn, the capacitance of the Mo S capacitor 14 is 20 pF, and the P-channel MO constituting the next stage CMOS inverter 13
The gains W/L of the S transistor and N channel MOS transistor are 200 μm/3°θ μm and 100 μm, respectively.
/1.8 μm, and the delay time is distributed from 100 to 250 ns depending on the gain of the inverter 12.

[Means for solving the problem] According to the present invention, first and second CMOS inverters are connected in cascade between input and output, and these first and second CMOS inverters are
A delay circuit is obtained, which includes a capacitive element connected between a connection point of a MOS inverter and a fixed potential, and a capacitance charging/discharging resistor is inserted into the source of one MOS transistor of a first CMOS inverter. Preferably, the capacitance charging/discharging resistor is a diffused resistor formed on a semiconductor substrate forming the first CMOS inverter.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1(a) is a delay circuit diagram showing one embodiment of the present invention. In this Figure 1(a), the same components as in Figure 3 are given the same symbols.

1(a) is different from FIG. 2 in that a resistor 18 made of a diffusion layer or the like is connected in series to the drain of the P-channel MOS transistor 16 of the CMOS inverter 12. This resistor 18 is used to delay charging of the MOS capacitor 14. The drain of an N-channel MOS transistor is connected to the drain of a P-channel MO transistor 16 via a resistor 18 to form a CMOS inverter.

Specific experimental results of such a delay circuit are shown in FIG. 1(b). In the figure, the horizontal axis represents the resistor 18, and the vertical axis represents the terminal 3-4.
The delay Q time (Vnn=4.5V, 5V) is shown. In either case, power supply voltage fluctuations have almost no effect on the delay time. Here, P channel MO8) transistor 16
and N-channel MOS) Gain W/L of transistor 17
are 300 fim/3. Ofim, 150tt
m/1.8 am, the capacitance of the MOS capacitor 14 is 20 pF.
Channel MO8) transistor, and N channel MOS
Transistor gain W/L is 200μm/3.0μ respectively
m.

The delay time is 100 μm/1.8 μm and varies from 100 to 250 ns depending on the value of the resistor 18.

FIG. 2 shows another embodiment of the invention.

In the figure, a resistor 21 is connected in series with the drain of an N-channel MOS transistor 17.

In this case as well, the resistor 21 is used as a delay in discharging the load capacitance, and has the same effect as the embodiment shown in FIG.

〔Effect of the invention〕

In this way, if the delay circuit according to the present invention is adopted, P-channel MO8) transistor or N-channel MOS)
While the ON resistance of a transistor is about several +Ω,
Since the built-in resistance is set to several tens of ohms, the influence of power supply fluctuations on the delay circuit section can be suppressed to less than 1%. Therefore, if the power supply fluctuation is guaranteed to be around 10%, the delay time fluctuation of a delay circuit with a conventional structure is directly affected by the power supply fluctuation of the ON resistance of a MOS transistor, and the result is around 10%.
In the delay circuit according to the present invention, the difference is only about 1%. In addition, temperature fluctuations in the fabricated resistor are hardly affected, and if the resistor layer is made large, manufacturing variations can be sufficiently reduced.

As described above, the present invention provides an easy-to-use device with small power supply fluctuations or temperature fluctuations, that is, small fluctuations after obtaining a sample for the user.

61

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram according to one embodiment of the present invention, FIG. 1(b) is a graph showing characteristics of one embodiment according to the present invention, and FIG. 2 is a circuit diagram of another embodiment of the present invention. , FIG. 3(a) is a circuit diagram showing a conventional delay circuit, and FIG. 3(b) is a graph showing characteristics of the conventional delay circuit. 3...Input terminal, 15...Terminal, 4.
...Output terminal, 10...High potential terminal, 1
1...Low potential terminal, 12.13...C
MOS inverter circuit, 14...MOS capacitor, 16.19...P channel MOS transistor, 17,20...N channel MO8) transistor, 18.21... ··resistance.

Claims (1)

[Claims] The first CMOS inverter includes first and second CMOS inverters connected in cascade between input and output, and a capacitive element connected between a connection point of these first and second CMOS inverters and a fixed potential point, A CM characterized in that a resistor is inserted between the drain of at least one transistor constituting the CMOS inverter and the capacitive element.
OS delay circuit.