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JPS57132425A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57132425A
JPS57132425A JP56018731A JP1873181A JPS57132425A JP S57132425 A JPS57132425 A JP S57132425A JP 56018731 A JP56018731 A JP 56018731A JP 1873181 A JP1873181 A JP 1873181A JP S57132425 A JPS57132425 A JP S57132425A
Authority
JP
Japan
Prior art keywords
transistor
output terminal
vds
conducting
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56018731A
Other languages
Japanese (ja)
Inventor
Tadashi Nakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56018731A priority Critical patent/JPS57132425A/en
Publication of JPS57132425A publication Critical patent/JPS57132425A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce influence by variance on the process, and to obtain a stable output characteristic, by inserting a resistance between a load driving buffer and an output terminal. CONSTITUTION:A resistance R1 is inserted between a connecting point of the drains of a P channel transistor T1 and an N channel transistor T2, and an output terminal 1. When a current flowing in the transistor T1 is denoted as I2 in a state that the transistor T1 is conducting, a potential difference against the ground potential VDD of the output terminal 1 becomes VDS+R1.I2 (in the expression, VDS denotes a potential difference between the source and the drain in a state that the transistor T1 is conducting). Therefore, when the transistor T1 is designed so as to satisfy VDS<<R1.I2, I2 is nearly decided by R1 and an outer load connected to the output terminal 1. This condition is realized easily by a shape of the transistor T1.
JP56018731A 1981-02-10 1981-02-10 Semiconductor device Pending JPS57132425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56018731A JPS57132425A (en) 1981-02-10 1981-02-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56018731A JPS57132425A (en) 1981-02-10 1981-02-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57132425A true JPS57132425A (en) 1982-08-16

Family

ID=11979809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56018731A Pending JPS57132425A (en) 1981-02-10 1981-02-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57132425A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63217820A (en) * 1987-03-06 1988-09-09 Nec Corp Cmos delay circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5351954A (en) * 1976-10-21 1978-05-11 Nippon Precision Circuits Cmos ic

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5351954A (en) * 1976-10-21 1978-05-11 Nippon Precision Circuits Cmos ic

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63217820A (en) * 1987-03-06 1988-09-09 Nec Corp Cmos delay circuit

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