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FR2296311A1 - Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over - Google Patents

Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over

Info

Publication number
FR2296311A1
FR2296311A1 FR7536058A FR7536058A FR2296311A1 FR 2296311 A1 FR2296311 A1 FR 2296311A1 FR 7536058 A FR7536058 A FR 7536058A FR 7536058 A FR7536058 A FR 7536058A FR 2296311 A1 FR2296311 A1 FR 2296311A1
Authority
FR
France
Prior art keywords
transistor
switching
integrated circuit
negative resistance
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7536058A
Other languages
French (fr)
Inventor
Algirdas J Gruodis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2296311A1 publication Critical patent/FR2296311A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

The complementary metal-oxide-semiconductor technology is used to produce an integrated circuit with a negative resistance characteristic under voltage application to a given circuit region. A metal-oxide-semiconductor transistor of a first channel type has its gate connected to the switching nodes and its source-drain path in series with a load to operating voltage source. A second such transistor of opposite channel type has its source-drain path connecting the switching node to the operating voltage source terminal, coupled to the load. This second transistor gate is connected to the junction point of the load and the first transistor. Thus the application of a voltage to a given region at the switching node the source-drain path of the second transistor becomes conductive.
FR7536058A 1974-12-24 1975-11-19 Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over Withdrawn FR2296311A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53606074A 1974-12-24 1974-12-24

Publications (1)

Publication Number Publication Date
FR2296311A1 true FR2296311A1 (en) 1976-07-23

Family

ID=24136962

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7536058A Withdrawn FR2296311A1 (en) 1974-12-24 1975-11-19 Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over

Country Status (2)

Country Link
JP (1) JPS5178683A (en)
FR (1) FR2296311A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2402973A1 (en) * 1977-09-08 1979-04-06 Ibm IMPROVED LOGIC OR CIRCUIT FOR PROGRAMMED LOGIC NETWORKS
FR2499788A1 (en) * 1981-02-06 1982-08-13 Rca Corp PULSE GENERATOR CIRCUIT USING POWER SOURCE AND MEMORY ASSEMBLY USING SUCH CIRCUIT
FR2838257A1 (en) * 2002-03-19 2003-10-10 Hewlett Packard Co PSEUDO-NMOS LOGIC COMPRISING A FEEDBACK CONTROLLER

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2402973A1 (en) * 1977-09-08 1979-04-06 Ibm IMPROVED LOGIC OR CIRCUIT FOR PROGRAMMED LOGIC NETWORKS
FR2499788A1 (en) * 1981-02-06 1982-08-13 Rca Corp PULSE GENERATOR CIRCUIT USING POWER SOURCE AND MEMORY ASSEMBLY USING SUCH CIRCUIT
FR2838257A1 (en) * 2002-03-19 2003-10-10 Hewlett Packard Co PSEUDO-NMOS LOGIC COMPRISING A FEEDBACK CONTROLLER

Also Published As

Publication number Publication date
JPS5178683A (en) 1976-07-08

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Legal Events

Date Code Title Description
ST Notification of lapse