JPS6331176A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPS6331176A JPS6331176A JP61174767A JP17476786A JPS6331176A JP S6331176 A JPS6331176 A JP S6331176A JP 61174767 A JP61174767 A JP 61174767A JP 17476786 A JP17476786 A JP 17476786A JP S6331176 A JPS6331176 A JP S6331176A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- crystal layer
- region
- concentration
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 230000003287 optical effect Effects 0.000 title claims description 20
- 239000013078 crystal Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 229910001297 Zn alloy Inorganic materials 0.000 abstract description 2
- SAOPTAQUONRHEV-UHFFFAOYSA-N gold zinc Chemical compound [Zn].[Au] SAOPTAQUONRHEV-UHFFFAOYSA-N 0.000 abstract description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical group [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 14
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 239000007791 liquid phase Substances 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
インジウム−ガリウム−砒素（ＩｎＧａＡｓ）系の化合
物半導体結晶を用いた特に長波長の光通信方式に用いる
光半導体受光素子の高信頼化を図ったもので、特に素子
を形成するために積層形成されている結晶層の最上層上
に、該最上層よりキャリア濃度を高濃度とした高濃度層
を一層余分に設けるとともに、該形成した高濃度層の受
光部の周辺部、即ち空乏層発生領域をエツチング除去す
ることで、その素子形成のために設けた最上層のエピタ
キシ中ル層とその上に形成する絶縁膜との界面電流の低
減を図り、表面リーク電流の低下を図る。[Detailed Description of the Invention] [Summary] This is an optical semiconductor light-receiving element that uses an indium-gallium-arsenide (InGaAs)-based compound semiconductor crystal and is used in particularly long-wavelength optical communication systems. On the top layer of the crystal layers stacked to form an element, an extra high concentration layer with a higher carrier concentration than the top layer is provided, and the light receiving part of the formed high concentration layer is By etching away the peripheral area, that is, the region where the depletion layer occurs, it is possible to reduce the interfacial current between the uppermost epitaxy intermediate layer provided for the device formation and the insulating film formed on it, and reduce the surface leakage current. We aim to reduce the
本発明はＩｎＧａＡｓ系の化合物半導体結晶を用いた半
導体受光素子に係り、特に長波長の光通信方式に用いる
光半導体受光素子に関する。The present invention relates to a semiconductor light-receiving element using an InGaAs-based compound semiconductor crystal, and more particularly to an optical semiconductor light-receiving element used in a long wavelength optical communication system.
ＩｎＧａＡｓ系化合物半導体結晶を用いた光半導体受光
素子は、外部より光を導入しない時、熱電子放射や、漏
れ抵抗によって電流が流れるといった暗電流の発生が少
なく 、１．５５μｍの波長帯での入射光子数に対する
放出光電子数の比、即ち量子効率も高いことから従来の
Ｇｅ受光素子等の素子に代わり、長波長光通信用受光素
子として最近注目されている。Optical semiconductor light-receiving elements using InGaAs-based compound semiconductor crystals generate little dark current, such as thermionic emission or current flow due to leakage resistance, when no light is introduced from the outside, and can detect light incident in the 1.55 μm wavelength band. Since the ratio of the number of emitted photoelectrons to the number of photons, that is, the quantum efficiency is also high, it has recently attracted attention as a light-receiving element for long-wavelength optical communications in place of devices such as conventional Ge light-receiving elements.
そのため、長波長光通信方式に用いられるＩ ｎＧａＡ
ｓ系受光素子は高信頼度のものが要求される傾向にあり
、素子表面での電流コントロールが重要な課題となる。Therefore, InGaA used in long wavelength optical communication systems
S-based light receiving elements tend to be required to be highly reliable, and current control on the element surface becomes an important issue.
特に素子形成のために設けた最上層のエピタキシャル層
と、その上に形成する絶縁膜との界面電流の低減が必要
となる。In particular, it is necessary to reduce the interfacial current between the uppermost epitaxial layer provided for element formation and the insulating film formed thereon.
従来、このようなｒｎＧａＡｓＰ系化合物半導体結晶を
用いた光半導体装置は、第２図に示すようにＮ型のＩｎ
Ｐ基扱基土１上−ＩｎＰのバッファ層２が形成され、更
にその上にＮ型のＩｎＧａＡｓ結晶層が活性層３として
形成され、更にその上にＮ”ｌｎＰ結晶層４が形成され
ている。Conventionally, optical semiconductor devices using such rnGaAsP-based compound semiconductor crystals have been manufactured using N-type In as shown in FIG.
An InP buffer layer 2 is formed on the P-based substrate 1, an N-type InGaAs crystal layer is formed as an active layer 3 on top of the buffer layer 2, and an N''lnP crystal layer 4 is formed on top of the active layer 3. .
更にこのＮ”ｌｎＰ結晶層４内にＳｉ原子がイオン注入
された後、該注入されたＳｉ原子の活性化を目的として
基板を熱処理して表面にリーク電流が流れないようにす
るためのチャネルストッパ層５が設けられている。Furthermore, after Si atoms are ion-implanted into this N''lnP crystal layer 4, a channel stopper is provided to heat the substrate for the purpose of activating the implanted Si atoms and to prevent leakage current from flowing to the surface. A layer 5 is provided.
更にＮ” ＩｎＰ結晶層４上には、窒化５ｔｌｌｌ！よ
りなる拡散用マスク６が形成され、この拡散用マスク６
を用いて、Ｐ型の不純物原子である亜鉛（Ｚｎ）原子が
導入されて活性層３にＰＮ接合部７が形成され、このＰ
Ｎ接合部７の上部には窒化Ｓｉ膜よりなる反射防止膜８
が形成され、このＰ型の不純物原子の導入層９に接触す
るように電極１０が形成されている。Furthermore, a diffusion mask 6 made of nitride 5tllll! is formed on the N'' InP crystal layer 4, and this diffusion mask 6
Zinc (Zn) atoms, which are P-type impurity atoms, are introduced into the active layer 3 to form a PN junction 7.
An antireflection film 8 made of a Si nitride film is provided on the upper part of the N junction part 7.
is formed, and an electrode 10 is formed so as to be in contact with this layer 9 into which P-type impurity atoms are introduced.
ところで、上記したＳｉ原子によるチャネルストッパ層
５は、Ｓｉ原子が選択的にイオン注入された後、このＳ
ｉ原子を活性化するために基板１を、約６５０℃の温度
で熱処理している。By the way, the above-mentioned channel stopper layer 5 made of Si atoms is formed after Si atoms are selectively ion-implanted.
The substrate 1 is heat treated at a temperature of about 650° C. to activate the i atoms.
そのため、選択イオン注入工程とその後の高温熱処理工
程の２工程の処理工程が必要であり、また高温熱処理工
程のために、積層形成されている活性Ｎ３やＮ“ＩｎＰ
結晶層４等のエピタキシャル結晶層の結晶性が劣化し、
格子欠陥や格子不整合等の不都合が生じていた。Therefore, two processing steps are required: a selective ion implantation step and a subsequent high-temperature heat treatment step. In addition, for the high-temperature heat treatment step, the active N3 and N"InP
The crystallinity of the epitaxial crystal layer such as crystal layer 4 deteriorates,
Problems such as lattice defects and lattice mismatches have occurred.
本発明は上記した問題点を除去し、工程を短縮してかつ
素子の表面リーク電流の減少を図った光半導体装置の提
供を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an optical semiconductor device that eliminates the above-mentioned problems, shortens the process, and reduces surface leakage current of the device.
（問題点を解決するための手段〕
本発明の光半導体装置は、素子形成のために化合物半導
体基板上に積層形成された結晶層の最上層上に連続して
、該最上層よりキャリア濃度の大きい高濃度結晶層を設
け、該最上層の結晶層に形成される空乏層発生領域に対
応する前記高濃度層の領域が除去されている。(Means for Solving the Problems) The optical semiconductor device of the present invention has a structure in which carrier concentration is lowered continuously on the uppermost layer of a crystal layer stacked on a compound semiconductor substrate for device formation. A large high concentration crystal layer is provided, and a region of the high concentration layer corresponding to a depletion layer generation region formed in the uppermost crystal layer is removed.
本発明の光半導体装置は、装置を形成する最上層の結晶
層上に該結晶層よりキャリア濃度の大きい結晶層を設け
、この結晶層をその下の最上層の結晶層に形成される空
乏層形成領域に対応する領域を除去する。In the optical semiconductor device of the present invention, a crystal layer having a higher carrier concentration than the crystal layer is provided on the uppermost crystal layer forming the device, and this crystal layer is used as a depletion layer formed in the uppermost crystal layer below. A region corresponding to the formation region is removed.
このようにして従来、素子を形成する最上層の化合物半
導体結晶層と、その上に形成される絶縁膜との界面で発
生する表面リーク電流をストップさせるための、Ｓｉ原
子のイオン注入法によるチャネルストッパの形成の熱処
理によって、基板上に形成された結晶層の歪みや、格子
不整合の発生を無くするようにする。In this way, in order to stop the surface leakage current that occurs at the interface between the uppermost compound semiconductor crystal layer that forms an element and the insulating film formed thereon, a channel is created using the ion implantation method of Si atoms. The heat treatment for forming the stopper eliminates distortion of the crystal layer formed on the substrate and the occurrence of lattice mismatch.
以下、図面を用いて本発明の一実施例につき詳細に説明
する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図に示すように、本発明の光半導体装置は、Ｎ型の
ＩｎＰよりなる化合物半導体基板１上にＮ−ＩｎＰの結
晶層２が液相エピタキシャル法で形成され、更にその上
にＩｎＧａＡｓ層よりなる活性層３と、更にその上にＮ
＋型のＩｎＰよりなる結晶層４が液相エピタキシャル成
長法によってそれぞれ形成されており、ここ迄は従来の
装置と同じである。As shown in FIG. 1, the optical semiconductor device of the present invention includes an N-InP crystal layer 2 formed by a liquid phase epitaxial method on a compound semiconductor substrate 1 made of N-type InP, and an InGaAs layer on top of the N-InP crystal layer 2. an active layer 3 consisting of
Crystal layers 4 made of +-type InP are each formed by liquid phase epitaxial growth, and up to this point the device is the same as the conventional device.
次いで該基板上にキャリア濃度が１０／ｃｍ３以上の高
濃度のＩｎＧａＡｓ、或いはＩｎＧａＡｓＰの高濃度層
１１が一層余分にエピタキシャル成長されている。Next, an extra high concentration layer 11 of InGaAs or InGaAsP with a carrier concentration of 10/cm<3> or more is epitaxially grown on the substrate.
そして素子形成のための最上層となるＩｎＰの結晶層４
に於いて空乏層が拡がる領域上の前記形成したＩｎＧａ
Ａｓ、或いはＩｎＧａＡｓＰの高濃度層１１がホトリソ
グラフィ法を用いた選択エツチングにより、選択的に除
去されている。And an InP crystal layer 4 which becomes the top layer for forming the element.
The formed InGa on the region where the depletion layer expands in
The high concentration layer 11 of As or InGaAsP is selectively removed by selective etching using photolithography.
このようにした状態で、該基板上に窒化Ｓｉ膜よりなる
拡散用マスク６を用いてＰ型の不純物原子である亜鉛（
Ｚｎ）原子を拡散して、Ｐ型頭域９が形成され、活性層
３領域内にＰＮ接合部７が形成されている。In this state, using a diffusion mask 6 made of a Si nitride film on the substrate, zinc (
By diffusing Zn) atoms, a P-type head region 9 is formed and a PN junction 7 is formed in the active layer 3 region.
更にＰ−Ｎ接合部７上の受光部領域上に窒化Ｓｉ膜より
なる反射防止膜８が蒸着により形成された後、前記形成
した拡散用マスク層６上に金−亜鉛合金よりなる電極１
０が蒸着及びホトリソグラフィ法を用いて形成されてい
る。Furthermore, after an antireflection film 8 made of a Si nitride film is formed by vapor deposition on the light receiving area on the P-N junction 7, an electrode 1 made of a gold-zinc alloy is deposited on the diffusion mask layer 6 formed above.
0 is formed using vapor deposition and photolithography methods.
このような本発明の構造の光半導体装置によれば、従来
の装置に比較して、素子形成のために行う液相エピタキ
シャル成長法を用いて最上層の結晶層４の上に、更に一
層高濃度のＩｎＧａＡｓ−、或いはＩｎＧａＡｓＰの高
濃度結晶Ｊｉｆｌｌを連続的に容易に形成することがで
きる。According to the optical semiconductor device having such a structure of the present invention, compared to conventional devices, even higher concentration is grown on the top crystal layer 4 using the liquid phase epitaxial growth method performed for element formation. A high-concentration crystal Jifll of InGaAs- or InGaAsP can be easily and continuously formed.
またその後のホトリソグラフィ法を用いた高濃度結晶層
１１のエツチング工程も簡単な工程である。Further, the subsequent etching process of the highly concentrated crystal layer 11 using photolithography is also a simple process.
従って従来の光半導体装置に於けるように、Ｓｉのチャ
ネルストンパ形成の際に、基板の加熱による熱歪みの現
象も除去でき、高信頼度の半導体装置が得られる。Therefore, as in the conventional optical semiconductor device, the phenomenon of thermal distortion due to heating of the substrate can be eliminated when forming the Si channel stopper, and a highly reliable semiconductor device can be obtained.
以上述べたように、本発明の光半導体装置によれば、選
択イオン打ち込み工程を液相エピタキシャル成長工程と
、エツチング工程に切り換えることができ、この液相エ
ピタキシャル成長工程は素子形成のエビタキシャル工程
に引き続いて行われるため、工程が複雑でなく簡単に行
える。As described above, according to the optical semiconductor device of the present invention, the selective ion implantation process can be switched to a liquid phase epitaxial growth process and an etching process, and this liquid phase epitaxial growth process is performed subsequent to the epitaxial process for device formation. The process is not complicated and can be easily performed.
またＳｉのイオン注入後の高温熱処理工程が無いため、
エピタキシャル結晶層の歪みがなく、高性能な光半導体
装置が得られる効果がある。Also, since there is no high-temperature heat treatment process after Si ion implantation,
There is an effect that a high-performance optical semiconductor device can be obtained without distortion of the epitaxial crystal layer.
第１図は本発明の光半導体装置の一実施例を示す断面図
、
第２図は従来の光半導体装置を示す断面図である。
図に於いて、
１はＮ型１ｎＰ基板、２はＮ−１ｎＰ結晶層、３は活性
層、４はＮ”ｌｎＰ結晶層、６は拡散用マスク、７はＰ
Ｎ接合部、８は反射防止膜、９はＰ型頭域、１０は電極
、１１は高濃度結晶層を示す。
ゼｐ胎１＋４杯客デ、、＃吻の
第１図
徒シぼそＸ任迄デｄ憧担
第２図FIG. 1 is a sectional view showing an embodiment of the optical semiconductor device of the present invention, and FIG. 2 is a sectional view showing a conventional optical semiconductor device. In the figure, 1 is an N-type 1nP substrate, 2 is an N-1nP crystal layer, 3 is an active layer, 4 is an N''lnP crystal layer, 6 is a diffusion mask, and 7 is a P
8 is an anti-reflection film, 9 is a P-type head region, 10 is an electrode, and 11 is a highly concentrated crystal layer. Zep womb 1 + 4 cups customer de...
Claims (1)
層（２、３、４）が積層形成され、該積層形成された最
上層の結晶層（４）上に、該最上層の結晶層（４）より
キャリア濃度の大きい高濃度結晶層（１１）が形成され
、前記最上層の結晶層（４）に形成される空乏層発生領
域に対応する前記高濃度結晶層（１１）の領域が除去さ
れていることを特徴とする光半導体装置。Semiconductor crystal layers (2, 3, 4) for forming elements are laminated on a compound semiconductor substrate (1), and on the laminated uppermost crystal layer (4), the uppermost crystal layer ( 4) A high concentration crystal layer (11) having a higher carrier concentration is formed, and a region of the high concentration crystal layer (11) corresponding to a depletion layer generation region formed in the uppermost crystal layer (4) is removed. An optical semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174767A JPS6331176A (en) | 1986-07-24 | 1986-07-24 | Optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174767A JPS6331176A (en) | 1986-07-24 | 1986-07-24 | Optical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331176A true JPS6331176A (en) | 1988-02-09 |
Family
ID=15984316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61174767A Pending JPS6331176A (en) | 1986-07-24 | 1986-07-24 | Optical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331176A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2466261A (en) * | 2008-12-17 | 2010-06-23 | Qinetiq Ltd | Semiconductor device and fabrication method |
-
1986
- 1986-07-24 JP JP61174767A patent/JPS6331176A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2466261A (en) * | 2008-12-17 | 2010-06-23 | Qinetiq Ltd | Semiconductor device and fabrication method |
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