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JPH02262379A - Semiconductor photodetector and manufacture thereof - Google Patents

Semiconductor photodetector and manufacture thereof

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Publication number
JPH02262379A
JPH02262379A JP1083556A JP8355689A JPH02262379A JP H02262379 A JPH02262379 A JP H02262379A JP 1083556 A JP1083556 A JP 1083556A JP 8355689 A JP8355689 A JP 8355689A JP H02262379 A JPH02262379 A JP H02262379A
Authority
JP
Japan
Prior art keywords
region
light
guard ring
semiconductor
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1083556A
Other languages
Japanese (ja)
Other versions
JP2793238B2 (en
Inventor
Masaaki Onomura
正明 小野村
Nobuo Suzuki
信夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1083556A priority Critical patent/JP2793238B2/en
Publication of JPH02262379A publication Critical patent/JPH02262379A/en
Application granted granted Critical
Publication of JP2793238B2 publication Critical patent/JP2793238B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To manufacture an APD, etc., capable of minimizing the dark current at a photodetecting part as well as simlifying the manufacturing processes by a method wherein a guard ring regions are formed encircling the photodetecting region not to be overlapped therewith and then the photodetecting region and the guard ring regions are connected respectively to different electrodes. CONSTITUTION:The title semiconductor photodetector is provided with the first conductivity type semiconductor substrates 11 to 16, the second conductivity type photodetecting region 17 formed on the surface layer 16 of the semiconductor substrates 11 to 16, guard rings 18 formed encircling the said photodetecting region 17 not to be overlapped with the region 17 while the said photodetecting region 17 and the guard ring regions 18 are connected respectively to different electrodes 22, 23. For example, an n-InP buffer layer 12, an b-InGaAs photoabsorption layer 13, an n-InGaAsP intermediate layer 14, an n-InP avalanche duplicated layer 15 and an n-InP layer 16 are successively and epitaxially deposited on an n<+>InP substrate 11 and then Cd is thermally diffused using an SiO2 film 21 as a mask so as to form the p<+>type photodetecting region 17 and the guard ring regions 18.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体受光装置及びその製造方法に係わり、
特にガードリング構造を有するブレーナ型へテロ接合ア
バランシェフォトダイオード(Avalanche P
hoto Diode、以下APDと略す)等の半導体
受光装置及びその製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor light receiving device and a method for manufacturing the same.
In particular, the Brehner-type heterojunction avalanche photodiode (Avalanche P) with a guard ring structure
The present invention relates to a semiconductor light receiving device such as a photo diode (hereinafter abbreviated as APD) and a method for manufacturing the same.

(従来の技術) 従来、光通信用の検出器としては、一般にフォトダイオ
ードが使用されているが、その中でも受信側マージンの
点で内部増幅機能を有するAPDが有用である。特に、
I nGaAs又はInGaAsPを光吸収層に用い、
InPを増倍層に用いたAPDは、格子整合したヘテロ
接合が可能であり、且つ石英系光ファイバーの低損失域
である 1.1〜1.6μm帯に受信感度を持つ。この
ため、長距離大容量光通信の検出器として有望であり、
その研究開発が盛んに進められている。
(Prior Art) Conventionally, photodiodes are generally used as detectors for optical communication, but among them, APDs having an internal amplification function are useful from the viewpoint of margin on the receiving side. especially,
Using InGaAs or InGaAsP for the light absorption layer,
An APD using InP as a multiplication layer is capable of forming a lattice-matched heterojunction, and has reception sensitivity in the 1.1-1.6 μm band, which is the low-loss region of silica-based optical fibers. Therefore, it is promising as a detector for long-distance, high-capacity optical communication.
Research and development is actively underway.

従来のAPD構造の一例(特開昭6O−19878fi
号)を第8図に示す。n”−1nP基板81の上にn−
1nPバッファ層82.n−−InGaAs光吸収層8
3.n−InGaAsP中間層84.n−InPアバラ
ンシェ増倍層85及びn−−InP層86を順次形成し
た半導体多層膜に、熱拡散或いはイオン注入により、階
段型pn接合を有するp+型導電領域の受光領域87が
形成され、この受光領域87の周囲に傾斜型pn接合を
有するp型導電領域の第1のガードリング領域88が一
部重なるように形成されている。さらに、第1のガード
リング領域88の周囲に、第1のガードリング領域88
より接合深さが浅い第2のガードリング領域89が一部
重なるように形成されている。第1のガードリング領域
88は階段型pn接合のエツジブレイクを防ぐため、第
2のガードリング領域89は第1のガードリング領域8
8のエツジブレイクを防ぐためのものである。なお、9
1は透明絶縁膜、92は絶縁膜、93.94は電極を示
している。
An example of a conventional APD structure (Japanese Patent Application Laid-Open No. 60-19878fi
(No.) is shown in Figure 8. n”-1nP substrate 81
1nP buffer layer 82. n--InGaAs light absorption layer 8
3. n-InGaAsP intermediate layer 84. A light-receiving region 87 of a p+ type conductive region having a stepped pn junction is formed in a semiconductor multilayer film in which an n-InP avalanche multiplication layer 85 and an n--InP layer 86 are sequentially formed by thermal diffusion or ion implantation. A first guard ring region 88, which is a p-type conductive region having a sloped pn junction, is formed around the light receiving region 87 so as to partially overlap with the first guard ring region 88. Further, a first guard ring region 88 is formed around the first guard ring region 88.
A second guard ring region 89 having a shallower junction depth is formed so as to partially overlap. The first guard ring region 88 prevents edge break of the stepped pn junction, and the second guard ring region 89 serves as the first guard ring region 8.
This is to prevent the edge break of 8. In addition, 9
1 is a transparent insulating film, 92 is an insulating film, and 93 and 94 are electrodes.

しかしながら、この種のAPDにあっては次のような問
題があった。即ち、2つのガードリングは形成条件が異
なるため2回のイオン注入工程を必要とし、その活性化
と拡散のために高温(例えば750℃)の熱処理工程を
必要とする。
However, this type of APD has the following problems. That is, since the two guard rings have different formation conditions, two ion implantation steps are required, and a high temperature (for example, 750° C.) heat treatment step is required for activation and diffusion.

また、受光部、第1及び第2のガードリング部に対し、
それぞれのpn接合位置合わせマージンをとるため、受
光部径に比べてpn接合面積が大きくなり、接合容量や
暗電流の増加を招いていた。
In addition, for the light receiving section, the first and second guard ring sections,
In order to provide a margin for alignment of each pn junction, the pn junction area becomes larger than the diameter of the light receiving portion, leading to an increase in junction capacitance and dark current.

(発明が解決しようとする課題) このように従来技術によるガードリング形成は、製造工
程が複雑であるばかりか、注入イオンの活性化のために
エピタキシャル成長温度よりも高温にさらす必要があり
半導体基板の品質劣化の原因になる。また、ガードリン
グ部に起因する暗電流が受光部に起因する暗電流と共に
同じ電極を通じて流れるため、暗電流の増大の原因にな
る。
(Problems to be Solved by the Invention) In this way, forming a guard ring using the conventional technology not only requires a complicated manufacturing process, but also requires exposing the semiconductor substrate to a higher temperature than the epitaxial growth temperature in order to activate the implanted ions. This may cause quality deterioration. Furthermore, the dark current caused by the guard ring portion flows through the same electrode as the dark current caused by the light receiving portion, which causes an increase in dark current.

本発明は、上記事情を考慮してなされたもので、その目
的とするところは、受光部の暗電流を最小限に抑えるこ
とができ、且つ製造工程の簡略化をはかり得る半導体受
光装置及びその製造方法を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor light receiving device and its semiconductor light receiving device that can minimize the dark current in the light receiving section and simplify the manufacturing process. The purpose is to provide a manufacturing method.

[発明の構成] (課題を解決するための手段) 本発明の骨子は、ガードリング部を受光部のpn接合の
外周部分に重ねて形成するのではなく、受光部の外周部
と重ならない領域に受光部のpn接合形成と同時に形成
し、受光部及びガードリング部をそれぞれ異なる電極に
接続することにある。
[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is that the guard ring portion is not formed overlapping the outer peripheral portion of the pn junction of the light receiving portion, but is formed in an area that does not overlap with the outer peripheral portion of the light receiving portion. The method is to form the pn junction simultaneously with the formation of the pn junction of the light receiving part, and to connect the light receiving part and the guard ring part to different electrodes.

前述したように、APDは高電圧を加えて用いるためp
n接合近傍で局所ブレイクが起こり易く、それを抑える
ためにイオン注入等で緩やかなpn接合であるガードリ
ングを形成する必要があった。ところが、本発明者等の
研究及び実験によれば、受光部の外周部の重ならない領
域にガードリングを形成したAPDに高電圧を加えても
局所ブレイクが起こらないことが確認された。
As mentioned above, since APD is used by applying high voltage, p
Local breakage tends to occur near the n-junction, and in order to suppress it, it is necessary to form a guard ring, which is a gentle pn junction, by ion implantation or the like. However, according to research and experiments conducted by the present inventors, it has been confirmed that local breakage does not occur even when a high voltage is applied to an APD in which a guard ring is formed in a non-overlapping area of the outer periphery of the light receiving part.

本発明はこのような点に着目し、第1導電型の半導体基
体と、この半導体基体の表面層に形成された第2導電型
の受光領域と、前記半導体基体の表面層に前記受光領域
を囲み該受光領域とは重ならないように形成されたガー
ドリング領域とを具備し、前記受光領域及びガードリン
グ領域をそれぞれ異なる電極に接続した3端子構造半導
体受光装置を提案するものである。
The present invention focuses on such points, and includes a semiconductor substrate of a first conductivity type, a light-receiving region of a second conductivity type formed on a surface layer of the semiconductor substrate, and a light-receiving region formed on the surface layer of the semiconductor substrate. The present invention proposes a three-terminal semiconductor light receiving device including a guard ring region formed so as not to overlap the surrounding light receiving region, and in which the light receiving region and the guard ring region are respectively connected to different electrodes.

また本発明は、上記半導体受光装置の製造方法において
、第1導電型の半導体基体の表面層に第2導電型不純物
を導入し、第2導電型の受光領域及び該受光領域を囲む
第2導電型のガードリング領域を同時に形成し、次いで
前記受光領域及びガードリング領域にそれぞれ異なる電
極を接続するようにした方法である。
The present invention also provides a method for manufacturing a semiconductor light receiving device, in which impurities of a second conductivity type are introduced into the surface layer of a semiconductor substrate of a first conductivity type, and a light receiving region of a second conductivity type and a second conductive region surrounding the light receiving region are provided. In this method, a guard ring region of the mold is formed at the same time, and then different electrodes are connected to the light receiving region and the guard ring region, respectively.

(作用) 本発明によれば、高電界がかかるpn接合近傍で起こる
局所ブレイクを防ぐために形成するガードリングを、従
来のように受光部外周に一部を重ねて設けるのではなく
、受光部外周側の重ならない領域に設け、受光部とガー
ドリング部は異なる電極に接続して独立に電圧を印加し
ている。このため、ガードリング部に起因する暗電流が
受光部に流れることはなく、第7図に示すように受光部
に流れる暗電流を低減することができる。なお、動作状
態においては、独立したガードリング部の電界によって
受光部エツジでの横方向にのびる高電界の発生を抑える
ことができ、これにより受光部の階段型pn接合のエツ
ジブレイクを防ぐことが可能となる。
(Function) According to the present invention, the guard ring formed in order to prevent local breakage that occurs near the pn junction where a high electric field is applied is not provided partially overlapping the outer periphery of the light receiving part as in the conventional method, but instead of providing a guard ring around the outer periphery of the light receiving part. The light-receiving part and the guard ring part are connected to different electrodes and voltages are applied independently. Therefore, dark current caused by the guard ring portion does not flow to the light receiving portion, and the dark current flowing to the light receiving portion can be reduced as shown in FIG. 7. In addition, in the operating state, the electric field of the independent guard ring part can suppress the generation of a high electric field extending in the lateral direction at the edge of the light receiving part, thereby preventing the edge break of the stepped pn junction in the light receiving part. It becomes possible.

また、従来のようなpn接合の位置合わせを行わなくて
も、例えば1回の熱拡散により受光部及びガードリング
部の形成が行え、さらにイオン注入後の熱処理のような
高温プロセスを必ずしも必要としない。また、半導体結
晶成長時に反対導電型半導体層を形成しイオン注入によ
って受光部とガードリング部を分離すれば、熱拡散プロ
セスさえ必ずしも必要としない。従って、製造工程が簡
略で、プロセスの低温化により結晶の熱変動を最小限に
抑えることが可能で、しかも低暗電流化が可能な半導体
受光装置が得られる。
Furthermore, the light receiving part and the guard ring part can be formed by one-time thermal diffusion without aligning the pn junction as in the conventional method, and there is no need for high-temperature processes such as heat treatment after ion implantation. do not. Moreover, if a semiconductor layer of opposite conductivity type is formed during semiconductor crystal growth and the light receiving part and the guard ring part are separated by ion implantation, even a thermal diffusion process is not necessarily required. Therefore, it is possible to obtain a semiconductor light-receiving device that has a simple manufacturing process, can minimize thermal fluctuations in the crystal by lowering the process temperature, and can also achieve low dark current.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

なお、以下の実施例では、InP/I nGaAsヘテ
ロ接合APDについて説明するが、他のへテロ接合AP
D及びホモ接合APD等についても全く同様であること
は容易に理解される。
In the following examples, InP/InGaAs heterojunction APD will be explained, but other heterojunction APDs will be described.
It is easily understood that the same holds true for D, homozygous APD, and the like.

第1図は本発明の第1の実施例に係わるAPDの概略構
造を示す断面図である。n”−InP基板11上に、n
−1nPバッファ層12を2am厚に、キャリア濃度が
1〜2 X 10”c+n −’のn−1nGaAs光
吸収層13を2am厚に、キャリア濃度が2 X 10
11016aのn−1nGaAsP中間層14を0.4
μm厚に、キャリア濃度が2〜3 X 10110l6
’のn−1nPアバランシ工増倍層15を1μm厚に、
キャリア濃度が1〜2 X 10”cm−’のn−−1
nP層16を0.8μm厚に、順次エピタキシャル成長
により形成した後、5in2膜21を絶縁マスクとして
、Cdを560℃の温度で15分間熱拡散し、所望の深
さにpn接合が位置するようにp+型の受光領域17及
びガードリング領域18を形成した。また、受光領域1
7表面の一部及びガードリング領域18の表面に、それ
ぞれが別電極としてとれるようにオーミック電極22.
23を形成し、さらに基板11の裏面側にオーミック電
極24を形成した。
FIG. 1 is a sectional view showing a schematic structure of an APD according to a first embodiment of the present invention. On the n''-InP substrate 11, n
The -1nP buffer layer 12 is 2 am thick, and the n-1n GaAs light absorption layer 13 with a carrier concentration of 1 to 2 x 10''c+n -' is 2 am thick, and the carrier concentration is 2 x 10
The n-1nGaAsP intermediate layer 14 of 11016a is 0.4
μm thick, carrier concentration is 2-3 x 10110l6
'n-1nP avalanche multiplier layer 15 with a thickness of 1 μm,
n−1 with a carrier concentration of 1 to 2 × 10” cm−1
After forming the nP layer 16 to a thickness of 0.8 μm by sequential epitaxial growth, using the 5in2 film 21 as an insulating mask, Cd was thermally diffused at a temperature of 560° C. for 15 minutes so that the pn junction was located at the desired depth. A p+ type light receiving region 17 and a guard ring region 18 were formed. In addition, light receiving area 1
7 and the surface of the guard ring region 18, ohmic electrodes 22.
23 was formed, and further an ohmic electrode 24 was formed on the back side of the substrate 11.

この実施例においては、イオン注入後行わないので活性
化のための高温熱処理を必要としない。第2図にこの実
施例によるAPDに高電圧を印加した場合の空乏層内の
電気力線を示す。
In this embodiment, high-temperature heat treatment for activation is not required because it is not performed after ion implantation. FIG. 2 shows lines of electric force within the depletion layer when a high voltage is applied to the APD according to this embodiment.

第2図において基板との間に印加する電圧の絶対値は受
光領域17よりガードリング領域18の方を小さくして
いる。この場合、ガードリング領域17に起因する電流
はガードリング領域17上に形成された電極23に流れ
るので、受光領域17の暗電流は低く抑えることができ
る。
In FIG. 2, the absolute value of the voltage applied between the guard ring region 18 and the substrate is smaller than that of the light receiving region 17. In this case, since the current caused by the guard ring region 17 flows to the electrode 23 formed on the guard ring region 17, the dark current in the light receiving region 17 can be suppressed to a low level.

また、ガードリング領域18によって形成される電界に
よって、受光領域17のエツジで横方向に伸びる高電界
を抑えることができ、その結果、受光領域17の階段型
pn接合のエツジブレイクを防ぐことができる。
Further, the electric field formed by the guard ring region 18 can suppress a high electric field extending laterally at the edge of the light receiving region 17, and as a result, edge breakage of the stepped pn junction in the light receiving region 17 can be prevented. .

かくして本実施例によれば、受光領域17とガードリン
グ領域18とを分離した構造を持つ3端子構造APDに
おいて、局所ブレイクを防ぐ効果が十分に得られ、ガー
ドリング領域18に起因する暗電流はガードリング領域
18上に形成された電極23を通じて流れるので受光領
域17上に形成された主電極21を通じて流れる暗電流
を低く抑えることができる。しかも、製造工程を簡略化
した低温プロセスで良好な素子特性を有する半導体受光
装置を実現することができる。従って、素子特性の優れ
た半導体受光装置を簡易に再現性よく実現することがで
き、その有用性は絶大である。
Thus, according to this embodiment, in a three-terminal APD having a structure in which the light receiving region 17 and the guard ring region 18 are separated, the effect of preventing local breakage is sufficiently obtained, and the dark current caused by the guard ring region 18 is reduced. Since the dark current flows through the electrode 23 formed on the guard ring region 18, the dark current flowing through the main electrode 21 formed on the light receiving region 17 can be suppressed to a low level. Furthermore, a semiconductor light receiving device having good device characteristics can be realized by a low-temperature process that simplifies the manufacturing process. Therefore, a semiconductor light-receiving device with excellent device characteristics can be easily realized with good reproducibility, and its usefulness is enormous.

第3図は本発明の第2の実施例に係わるAPDの概略構
造を示す断面図である。なお、第1図と同一部分には同
一符号を付して、その詳しい説明は省略する。
FIG. 3 is a sectional view showing a schematic structure of an APD according to a second embodiment of the present invention. Note that the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

この実施例では、n ”  I n P基板11上に、
各層12.〜,16を先の実施例と同じ条件で形成した
後、図示しないSiO2膜を絶縁マスクとして用いてガ
ードリングとなる領域の外周部にBeイオンを150k
VでI X 1013c111−2注入し、700℃で
20分の熱処理を行うことにより、イオン注入後の活性
化と拡散を行いガードリング領域(第2のガードリング
領域)19を形成し、イオン注入のためのSiO2膜を
取り除いた後に、新たに熱拡散のためにSiO2膜21
を絶縁マスクとして形成し、Cdを560℃の温度で1
5分間熱拡散し、所望の深さにp + n接合が位置す
るように受光領域17及びガードリング領域(第1のガ
ードリング領域)18を形成した。
In this embodiment, on the n'' I n P substrate 11,
Each layer 12. ~, 16 were formed under the same conditions as in the previous example, and then Be ions were applied to the outer periphery of the region that would become the guard ring at a rate of 150K using a SiO2 film (not shown) as an insulating mask.
By implanting IX 1013c111-2 at V and performing heat treatment at 700° C. for 20 minutes, activation and diffusion after ion implantation are performed to form a guard ring region (second guard ring region) 19, and the ion implantation is performed. After removing the SiO2 film 21 for heat diffusion, a new SiO2 film 21 is removed for heat diffusion.
was formed as an insulating mask, and Cd was heated to 1 at a temperature of 560°C.
Thermal diffusion was carried out for 5 minutes to form a light receiving region 17 and a guard ring region (first guard ring region) 18 such that the p + n junction was located at a desired depth.

第3図の構造は第1図のガードリング領域18の外周部
にイオン注入を行った構造であるが、これによってガー
ドリング領域18に受光領域17への印加電圧と絶対値
が同程度または僅かに高く電圧を印加できるようにした
ものである。第4図に本発明の第2の実施例によるAP
Dに高電圧を印加した場合の電気力線を示す。第4図に
おいて基板との間に印加する電圧の絶対値は受光領域1
7に比べてガードリング領域18の方が僅かに大きいか
同程度である。
The structure shown in FIG. 3 is a structure in which ions are implanted into the outer periphery of the guard ring region 18 shown in FIG. This allows a high voltage to be applied to the FIG. 4 shows an AP according to a second embodiment of the present invention.
The lines of electric force when a high voltage is applied to D are shown. In Fig. 4, the absolute value of the voltage applied between the substrate and the light receiving area 1 is
7, the guard ring region 18 is slightly larger or about the same size.

この場合も、ガードリング領域18によって形成される
電界によって、受光領域17のエツジで横方向に伸びる
高電界の発生を抑えることができ、これにより受光部p
n接合からの電界はアバランシェ増倍層から光吸収層ま
で一様に延びるようになり、また第1の実施例と同様に
ガードリング領域18に起因する電流はガードリング領
域18上に形成された電極23に流れるので、受光領域
17の暗電流は低く抑えることができる。
In this case as well, the electric field formed by the guard ring region 18 can suppress the generation of a high electric field extending laterally at the edge of the light receiving region 17.
The electric field from the n-junction now extends uniformly from the avalanche multiplication layer to the light absorption layer, and as in the first embodiment, the current caused by the guard ring region 18 is formed on the guard ring region 18. Since the dark current flows through the electrode 23, the dark current in the light receiving region 17 can be kept low.

第5図は本発明の第3の実施例に係わるAPDの概略構
造を示す断面図である。なお、第1図と同一部分には同
一符号を付して、その詳しい説明は省略する。
FIG. 5 is a sectional view showing a schematic structure of an APD according to a third embodiment of the present invention. Note that the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

この実施例では、ri“−InP基板11上に、各層1
2.〜,15を先の実施例と同じ条件で形成したのち、
続いてキャリア濃度が1〜2×10”cn+−’のn−
−1nP層16を0.2μm厚に、キャリア濃度がI 
X 10110l8’のp”−1nP層56を0.8μ
m厚に、順次エピタキシャル成長に・より形成した。次
いで、5in2膜21を絶縁マスクとして、■イオンを
100kV テI X 10”ell−2注入し、受光
領域17及びガードリング領域18の分離のための絶縁
部(高抵抗層)58を形成した。このイオン注入された
p型1nP領域56は400℃程度の熱処理により抵抗
率106Ω(至)以上の半絶縁領域58となる。また、
第5図では水素をイオン注入源として用いたが、この代
わりにn型不純物を用いてもよい。この場合、n型不純
物をイオン注入した後、活性化のための熱処理を行えば
、p4型受光領域17とイオン注入領域の界面では緩や
かなpn接合が形成されることになり、電界集中緩和が
期待できる。
In this embodiment, each layer 1 is placed on the ri"-InP substrate 11.
2. ~, 15 were formed under the same conditions as in the previous example, and then
Next, n− with a carrier concentration of 1 to 2×10”cn+−′
-1nP layer 16 is 0.2 μm thick, carrier concentration is I
X 10110l8'p''-1nP layer 56 is 0.8μ
It was formed by sequential epitaxial growth to a thickness of m. Next, using the 5 in 2 film 21 as an insulating mask, ions were implanted at 100 kV TE I x 10''ell-2 to form an insulating part (high resistance layer) 58 for separating the light receiving region 17 and the guard ring region 18 . This ion-implanted p-type 1nP region 56 becomes a semi-insulating region 58 with a resistivity of 106Ω (up to) or more by heat treatment at about 400°C.
Although hydrogen is used as the ion implantation source in FIG. 5, n-type impurities may be used instead. In this case, if heat treatment for activation is performed after ion-implanting the n-type impurity, a gentle p-n junction will be formed at the interface between the p4-type light-receiving region 17 and the ion-implanted region, and the electric field concentration will be relaxed. You can expect it.

第6図に本発明の第3の実施例によるAPDに高電圧を
印加した場合の電気力線を示す。第6図において基板と
の間に印加する電圧の絶対値は受光領域17とガードリ
ング領域18とで同程度である。
FIG. 6 shows lines of electric force when a high voltage is applied to the APD according to the third embodiment of the present invention. In FIG. 6, the absolute value of the voltage applied between the light receiving region 17 and the guard ring region 18 is approximately the same.

なお、本発明は上述した各実施例に限定されるものでは
ない。実施例ではI n P / I n G aAs
へテロ接合APDについて説明したが、他のへテロ接合
APDやホモ接合APD等に適用することもできる。即
ち、半導体多層膜を用いる代わりに、ゲルマニウムやシ
リコン等の基板の表面層に直接、受光領域やガードリン
グ領域を形成することも可能である。その他、本発明の
要旨を逸脱しない範囲で、種々変形して実施することが
できる。
Note that the present invention is not limited to the embodiments described above. In the example, I n P / I n GaAs
Although the description has been made regarding heterozygous APD, the present invention can also be applied to other heterozygous APDs, homozygous APDs, and the like. That is, instead of using a semiconductor multilayer film, it is also possible to form a light receiving region and a guard ring region directly on the surface layer of a substrate made of germanium, silicon, or the like. In addition, various modifications can be made without departing from the gist of the present invention.

[発明の効果コ 以上詳述したように本発明によれば、ガードリング部を
受光部のpn接合の外周部分に重ねて形成するのではな
く、受光部の外周部と重ならない領域に受光部のpn接
合形成と同時に形成し、受光部及びガードリング部をそ
れぞれ異なる電極に接続することにより、受光部上に形
成された電極を通じて流れる暗電流は低く抑えることが
できる。また、受光部のpn接合及びガードリング部の
pn接合を1回の拡散工程で形成できるので、製造工程
の簡略化をはかり得る。
[Effects of the Invention] As detailed above, according to the present invention, the guard ring portion is not formed overlapping the outer peripheral portion of the pn junction of the light receiving portion, but the light receiving portion is formed in an area that does not overlap with the outer peripheral portion of the light receiving portion. By forming the pn junction simultaneously with the formation of the pn junction and connecting the light receiving part and the guard ring part to different electrodes, the dark current flowing through the electrode formed on the light receiving part can be suppressed to a low level. Furthermore, since the pn junction of the light receiving part and the pn junction of the guard ring part can be formed in one diffusion process, the manufacturing process can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例に係わるAPDの概略構
造を示す断面図、第2図は第1の実施例のAPDに電圧
を印加したときの電気力線を示す模式図、第3図は本発
明の第2の実施例の概略構造を示す断面図、第4図は第
2の実施例における電気力線を示す模式図、第5図は本
発明の第3の実施例の概略構造を示す断面図、第6図は
第3の実施例における電気力線を示す模式図、第7図は
本発明のAPD及び従来のAPDの逆方向電圧印加にお
ける暗電流特性を示す特性図、第8図は従来のAPDの
概略構造を示す断面図である。 11−n” −1n P基板、12− n −1n P
バラフッ層、13・・・n−1nGaAs光吸収層、1
4−−・n −I n G a A s P中間層、1
5−n −1、nPアバランシェ増倍層、16・・・n
−−InP層、17・・・p+型層(受光領域) 18
・・・p1型層(第1のガードリング領域)、19・・
・p+型層(第2のガードリング領域)、21・・・絶
縁膜、22.23・・・p側電極、24・・・n側電極
、56−p”−1nP層、58−・・絶縁部(高抵抗層
)。 出願人代理人 弁理士 鈴 江 武 彦第1図 第5図 第6図 第3図 1I7図 ソ4 第8図
FIG. 1 is a sectional view showing a schematic structure of an APD according to a first embodiment of the present invention, FIG. 2 is a schematic diagram showing lines of electric force when voltage is applied to the APD of the first embodiment, and FIG. 3 is a cross-sectional view showing the schematic structure of the second embodiment of the present invention, FIG. 4 is a schematic diagram showing the lines of electric force in the second embodiment, and FIG. 5 is a schematic diagram of the third embodiment of the present invention. 6 is a schematic diagram showing the lines of electric force in the third embodiment; FIG. 7 is a characteristic diagram showing the dark current characteristics of the APD of the present invention and the conventional APD when reverse voltage is applied. , FIG. 8 is a cross-sectional view showing the schematic structure of a conventional APD. 11-n''-1n P substrate, 12-n-1n P
Rose fluorine layer, 13...n-1nGaAs light absorption layer, 1
4--・n-I n Ga As P middle layer, 1
5-n -1, nP avalanche multiplication layer, 16...n
--InP layer, 17...p+ type layer (light receiving area) 18
...p1 type layer (first guard ring region), 19...
・p+ type layer (second guard ring region), 21... insulating film, 22.23... p side electrode, 24... n side electrode, 56-p''-1nP layer, 58-... Insulating part (high resistance layer). Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 5 Figure 6 Figure 3 Figure 1I7 Figure 4 Figure 8

Claims (5)

【特許請求の範囲】[Claims] (1)第1導電型の半導体基体と、この半導体基体の表
面層に形成された第2導電型の受光領域と、前記半導体
基体の表面層に前記受光領域を囲み該受光領域とは重な
らないように形成されたガードリング領域とを具備し、
前記受光領域及びガードリング領域をそれぞれ異なる電
極に接続してなることを特徴とする半導体受光装置。
(1) A semiconductor substrate of a first conductivity type, a light-receiving region of a second conductivity type formed on a surface layer of the semiconductor substrate, and a surface layer of the semiconductor substrate surrounding the light-receiving region and not overlapping with the light-receiving region. and a guard ring area formed to
A semiconductor light-receiving device characterized in that the light-receiving region and the guard ring region are respectively connected to different electrodes.
(2)第1導電型の半導体基板と、この半導体基板上に
積層形成された少なくとも光吸収層及びアバランシェ増
倍層を含む第1導電型の半導体多層膜と、この半導体多
層膜の表面層に形成された第2導電型の受光領域と、前
記半導体多層膜の表面層に前記受光領域を囲み該領域と
は重ならないように形成されたガードリング領域とを具
備し、前記受光領域及びガードリング領域がそれぞれ独
立に電圧が印加されるように異なる電極に接続してなる
ことを特徴とする半導体受光装置。
(2) a semiconductor substrate of a first conductivity type, a semiconductor multilayer film of a first conductivity type including at least a light absorption layer and an avalanche multilayer film laminated on the semiconductor substrate, and a surface layer of the semiconductor multilayer film; The light-receiving region of the second conductivity type is formed, and a guard ring region is formed on the surface layer of the semiconductor multilayer film to surround the light-receiving region and not overlap with the region, and the light-receiving region and the guard ring are provided. A semiconductor light-receiving device characterized in that the regions are connected to different electrodes so that voltages are applied independently to each region.
(3)第1導電型の半導体基板と、この半導体基板上に
積層形成された少なくとも光吸収層及びアバランシェ増
倍層を含む第1導電型の半導体多層膜と、この半導体多
層膜上に形成された第2導電型の半導体膜と、この半導
体膜にリング状に形成され内側の受光領域と外側のガー
ドリング領域とを電気的に分離する高抵抗領域又は第1
導電型領域とを具備し、前記受光領域及びガードリング
領域をそれぞれ異なる電極に接続してなることを特徴と
する半導体受光装置。
(3) a semiconductor substrate of a first conductivity type; a semiconductor multilayer film of a first conductivity type including at least a light absorption layer and an avalanche multilayer layer formed on the semiconductor substrate; and a semiconductor multilayer film of a first conductivity type formed on the semiconductor multilayer film; a semiconductor film of a second conductivity type, and a high resistance region or a first high resistance region formed in a ring shape on this semiconductor film and electrically separating an inner light receiving region and an outer guard ring region.
What is claimed is: 1. A semiconductor light-receiving device, comprising: a conductivity type region, and the light-receiving region and the guard ring region are respectively connected to different electrodes.
(4)第1導電型の半導体基体の表面層に第2導電型不
純物を選択的に導入し、第2導電型の受光領域及び該受
光領域を囲む第2導電型のガードリング領域を同時に形
成する工程と、前記受光領域及びガードリング領域にそ
れぞれ異なる電極を接続する工程とを含むことを特徴と
する半導体受光装置の製造方法。
(4) Selectively introducing impurities of the second conductivity type into the surface layer of the semiconductor substrate of the first conductivity type, and simultaneously forming a light-receiving region of the second conductivity type and a guard ring region of the second conductivity type surrounding the light-receiving region. and connecting different electrodes to the light receiving region and the guard ring region, respectively.
(5)n型半導体基板上に少なくともn型光吸収層、n
型アバランシェ増倍層及び該増倍層と同種のp型半導体
層を順次成長する工程と、前記p型半導体層の受光部と
なる領域とガードリング部となる領域の間にH、D、H
e、Li、Be、Ne、Ar又はn型不純物の少なくと
も一つをイオン注入して、p型の受光領域とp型のガー
ドリング領域とを分離する工程と、前記n型半導体基板
、p型受光領域及びp型ガードリング領域のそれぞれに
異なる電極を接続する工程とを含むことを特徴とする半
導体受光装置の製造方法。
(5) At least an n-type light absorption layer on the n-type semiconductor substrate;
A step of sequentially growing a type avalanche multiplication layer and a p-type semiconductor layer of the same type as the multiplication layer, and forming H, D, H between the region of the p-type semiconductor layer that will become the light receiving part and the region that will become the guard ring part.
a step of ion-implanting at least one of e, Li, Be, Ne, Ar, or n-type impurity to separate a p-type light-receiving region and a p-type guard ring region; A method for manufacturing a semiconductor light receiving device, comprising the step of connecting different electrodes to each of the light receiving region and the p-type guard ring region.
JP1083556A 1989-03-31 1989-03-31 Semiconductor light receiving device and method of manufacturing the same Expired - Fee Related JP2793238B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1083556A JP2793238B2 (en) 1989-03-31 1989-03-31 Semiconductor light receiving device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1083556A JP2793238B2 (en) 1989-03-31 1989-03-31 Semiconductor light receiving device and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP10056687A Division JP2996943B2 (en) 1998-03-09 1998-03-09 Semiconductor light receiving device and method of manufacturing the same

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Publication Number Publication Date
JPH02262379A true JPH02262379A (en) 1990-10-25
JP2793238B2 JP2793238B2 (en) 1998-09-03

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724018B2 (en) 2001-09-06 2004-04-20 Sumitomo Electric Industries, Ltd. Zn1-xMgxSySe1-y pin-photodiode and Zn1-xMgxSySe1-y avalanche-photodiode
JP2007335596A (en) * 2006-06-14 2007-12-27 Hamamatsu Photonics Kk Photodiode array
CN106328752A (en) * 2016-11-14 2017-01-11 南通大学 Planar lateral collection structure indium gallium arsenic infrared detector chip
CN111863971A (en) * 2019-04-30 2020-10-30 阿聚尔斯佩西太阳能有限责任公司 Stacked high cut-off InGaAs semiconductor power diodes

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101931021A (en) * 2010-08-28 2010-12-29 湘潭大学 Single-photon avalanche diode and its 3D CMOS image sensor
CN102024863B (en) * 2010-10-11 2013-03-27 湘潭大学 High-speed enhanced ultraviolet silicon selective avalanche photodiode and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
JPS5057785A (en) * 1973-09-18 1975-05-20
JPS5687380A (en) * 1979-12-18 1981-07-15 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device for detection of radiant light
JPS60173882A (en) * 1984-02-20 1985-09-07 Nec Corp semiconductor equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057785A (en) * 1973-09-18 1975-05-20
JPS5687380A (en) * 1979-12-18 1981-07-15 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device for detection of radiant light
JPS60173882A (en) * 1984-02-20 1985-09-07 Nec Corp semiconductor equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724018B2 (en) 2001-09-06 2004-04-20 Sumitomo Electric Industries, Ltd. Zn1-xMgxSySe1-y pin-photodiode and Zn1-xMgxSySe1-y avalanche-photodiode
JP2007335596A (en) * 2006-06-14 2007-12-27 Hamamatsu Photonics Kk Photodiode array
JP4602287B2 (en) * 2006-06-14 2010-12-22 浜松ホトニクス株式会社 Photodiode array
CN106328752A (en) * 2016-11-14 2017-01-11 南通大学 Planar lateral collection structure indium gallium arsenic infrared detector chip
CN111863971A (en) * 2019-04-30 2020-10-30 阿聚尔斯佩西太阳能有限责任公司 Stacked high cut-off InGaAs semiconductor power diodes
CN111863971B (en) * 2019-04-30 2023-10-31 阿聚尔斯佩西太阳能有限责任公司 Stacked high-cut-off InGaAs semiconductor power diodes

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