JPS63283033A - Die bonding method - Google Patents
Die bonding methodInfo
- Publication number
- JPS63283033A JPS63283033A JP62116756A JP11675687A JPS63283033A JP S63283033 A JPS63283033 A JP S63283033A JP 62116756 A JP62116756 A JP 62116756A JP 11675687 A JP11675687 A JP 11675687A JP S63283033 A JPS63283033 A JP S63283033A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- capacitor
- gold
- circuit pattern
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は単板磁器コンデンサ等のダイボンディングによ
って搭載される電子・電気部品のダイボンディング方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a die bonding method for electronic/electrical components mounted by die bonding, such as single-plate ceramic capacitors.
従来、単板状をした磁器の両面に金メッキ等で電極を形
成した構成の単板磁器コンデンサを薄膜基板の回路パタ
ーン上にボンディングする方法として、第2図に示す方
法が行われている。即ち、単板磁器コンデンサ11の金
メッキされた電極の片面に共晶半田13を付着させてこ
れを薄膜基板12の所定回路パターン上に載置する一方
、薄膜基板12はホットプレート14上に載せて加熱さ
せ、この熱によって共晶半田13を溶融させ、単板磁器
コンデンサ11を薄膜基板12に接合させる方法である
。Conventionally, a method shown in FIG. 2 has been used to bond a single-plate porcelain capacitor, in which electrodes are formed by gold plating or the like on both sides of a single-plate porcelain plate, onto a circuit pattern on a thin film substrate. That is, eutectic solder 13 is attached to one side of the gold-plated electrode of the single-plate ceramic capacitor 11 and placed on a predetermined circuit pattern of the thin film substrate 12, while the thin film substrate 12 is placed on the hot plate 14. In this method, the single-plate ceramic capacitor 11 is bonded to the thin film substrate 12 by heating and melting the eutectic solder 13 by the heat.
〔発明が解決しようとする問題点]
上述した従来の共晶半田によるダイボンディング方法で
は、単板磁器コンデンサ11の側面に金メッキ電極のパ
リが生じていると、共晶半田13がこのパリに沿って上
側の金メッキ電極まで這い上がり、両電極がショートす
るという問題がある。[Problems to be Solved by the Invention] In the above-described conventional die bonding method using eutectic solder, if a ridge of the gold-plated electrode is formed on the side surface of the single-plate ceramic capacitor 11, the eutectic solder 13 will move along the edge. There is a problem in that the metal layer creeps up to the upper gold-plated electrode, causing a short circuit between the two electrodes.
また、単板磁器コンデンサ11の金メッキ電極より小さ
い寸法の回路パターン上にボンディングする際には、共
晶半田13が周囲に溢れて広がり、これが周辺のワイヤ
ボンディングの箇所まで流れてワイヤボンディングに支
障を来すという問題もあり、生産歩留りに悪影響を及ぼ
している。Furthermore, when bonding is performed on a circuit pattern with dimensions smaller than the gold-plated electrodes of the single-plate ceramic capacitor 11, the eutectic solder 13 overflows and spreads to the surrounding area, flowing to the surrounding wire bonding points and interfering with wire bonding. There is also the problem of overheating, which has a negative impact on production yields.
本発明は上述したような電極間のショート及び周辺位置
におけるワイヤボンディング不能等の問題を解決して良
好なボンディングを可能とするダイボンディング方法を
提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a die bonding method that solves the above-mentioned problems such as short circuits between electrodes and the inability to perform wire bonding at peripheral positions, and enables good bonding.
本発明のダイボンディング方法は、電子・電気部品に設
ける金メッキ電極を厚い金メッキ層で形成し、かつこの
金メッキ層を回路パターンに接触させた状態で電子・電
気部品を背後から所要の圧力で押圧しかつ加熱して、回
路パターンに熱圧着させることにより、共晶半田等の接
着部材を不要とし、この接着部材が原因とされる電極間
のショートや周辺への影響を防止するものである。In the die bonding method of the present invention, a gold-plated electrode to be provided on an electronic/electrical component is formed with a thick gold-plated layer, and the electronic/electrical component is pressed from behind with a required pressure while this gold-plated layer is in contact with a circuit pattern. By heating and thermocompression bonding to the circuit pattern, an adhesive member such as eutectic solder is not required, and short circuits between electrodes and effects on the surrounding area caused by the adhesive member are prevented.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明のダイボンディング方法の一実施例を示
す図である。FIG. 1 is a diagram showing an embodiment of the die bonding method of the present invention.
この方法は、先ず単板磁器コンデンサ1の両面に設ける
金メッキ電極を、その形成時に金メッキを充分に厚く(
約10〜12μm)なるように形成する。In this method, gold-plated electrodes are first provided on both sides of a single-plate ceramic capacitor 1, and the gold plating is applied to a sufficiently thick layer (
10 to 12 μm).
そして、このように構成された単板磁器コンデンサ1を
薄膜基板2の所要回路パターン上に載置する。これと同
時に、薄膜基板2を、温度300〜320°Cに加熱さ
れたホットプレート4上に載置させ全体を加熱する。Then, the single-plate ceramic capacitor 1 configured as described above is placed on the desired circuit pattern of the thin film substrate 2. At the same time, the thin film substrate 2 is placed on a hot plate 4 heated to a temperature of 300 to 320°C, and the whole is heated.
しかる上で、単板磁器コンデンサ1に近い寸法の角型形
状をしたサファイヤ製のウェッジ3を単板磁器コンデン
サ1の上面電極部に当接させ、かつこれに荷重1〜3K
g/mm2を加えて単板磁器コンデンサ1を薄膜基板2
に押圧させる。Then, a sapphire wedge 3 having a rectangular shape similar to the size of the single-plate ceramic capacitor 1 is brought into contact with the upper electrode part of the single-plate ceramic capacitor 1, and a load of 1 to 3K is applied to the wedge 3.
By adding g/mm2, the single plate porcelain capacitor 1 is connected to the thin film substrate 2.
to be pressed.
これにより、単板磁器コンデンサ1の下面側の金メッキ
電極の金メッキ層は溶融し、薄膜基板2の回路パターン
に熱圧着によって接合され、単板磁器コンデンサ1自体
が薄膜基板2に固着される。As a result, the gold-plated layer of the gold-plated electrode on the lower surface side of the single-plate ceramic capacitor 1 is melted and bonded to the circuit pattern of the thin-film substrate 2 by thermocompression bonding, and the single-plate ceramic capacitor 1 itself is fixed to the thin-film substrate 2.
したがって、この方法のダイボンディングによれば、単
板磁器コンデンサ1は、充分に厚く形成した金メッキ電
極の金メッキ層を熱と圧力で溶融して薄膜基板2の回路
パターンに熱圧着してボンディングを行っているので、
共晶半田等の接着材料を使用する必要はなく、この種の
接着材料が原因とされる両電極のショートが生じること
は全くない。また、この種の接着材料がコンデンサの周
囲のワイヤボンディング領域に溢れて広がることもなく
、ワイヤボンディング不能の発生を有効に防止すること
もできる。Therefore, according to this method of die bonding, the single-plate porcelain capacitor 1 is bonded by melting the gold plating layer of a sufficiently thick gold-plated electrode with heat and pressure and thermocompression bonding to the circuit pattern of the thin film substrate 2. Because
There is no need to use adhesive materials such as eutectic solder, and there is no possibility of short circuits between the electrodes caused by this type of adhesive material. Moreover, this type of adhesive material does not overflow and spread into the wire bonding area around the capacitor, and it is also possible to effectively prevent wire bonding from occurring.
なお、実施例では単板磁器コンデンサに本発明を適用し
た例を説明したが、同じまたは類似の形状の電子・電気
部品をダイボンディングする際にも同様に適用すること
ができる。In the embodiment, an example in which the present invention is applied to a single-plate ceramic capacitor has been described, but the present invention can be similarly applied to die bonding of electronic/electrical components having the same or similar shape.
以上説明したように本発明は、電子・電気部品の金メッ
キ電極を厚い金メッキ層で形成し、電子・電気部品を背
後から所要の圧力で押圧しかつ加熱して回路パターンに
熱圧着させるので、共晶半田等の接着部材を不要にし、
この接着部材が原因とされる電極間の短絡を防止すると
ともに接着部材のダイボンディング部材周辺部への広が
りにょるワイヤボンディングの支障を解消し、これによ
り良好なボンディングを実現して、この種のダイボンデ
ィング部材を搭載するハイブリッドICの歩留り向上を
図ることができる。As explained above, in the present invention, the gold-plated electrodes of electronic and electrical components are formed with a thick gold-plated layer, and the electronic and electrical components are pressed from behind with the required pressure and heated to thermocompression bond them to the circuit pattern. Eliminates the need for adhesive materials such as crystal solder,
In addition to preventing short circuits between electrodes caused by this adhesive material, it also eliminates problems with wire bonding caused by the adhesive material spreading around the die bonding material, thereby achieving good bonding and making it possible to It is possible to improve the yield of hybrid ICs equipped with die bonding members.
第1図は本発明のボンディング方法を示す斜視図、第2
図は従来のボンディング方法を示す斜視図である。
1.11・・・単板磁器コンデンサ、2,12・・・薄
膜基板、3・・・ウェッジ、4.14・・・ホットプレ
ート、13・・・共晶半田。Fig. 1 is a perspective view showing the bonding method of the present invention, Fig. 2 is a perspective view showing the bonding method of the present invention;
The figure is a perspective view showing a conventional bonding method. 1.11... Single plate ceramic capacitor, 2, 12... Thin film substrate, 3... Wedge, 4.14... Hot plate, 13... Eutectic solder.
Claims (1)
路パターンに直接ボンディングする電子・電気部品のダ
イボンディング方法において、前記金メッキ電極を厚い
金メッキ層で形成し、かつこの金メッキ層を回路パター
ンに接触させた状態で前記電子・電気部品を背後から所
要の圧力で押圧しかつ加熱して、前記回路パターンに熱
圧着させることを特徴とするダイボンディング方法。(1) In a die bonding method for electronic/electrical components that has gold-plated electrodes on both sides and directly bonds one side to a circuit pattern on a board, the gold-plated electrode is formed with a thick gold-plated layer, and this gold-plated layer is used as a circuit pattern. A die bonding method characterized in that the electronic/electrical component is pressed from behind with a predetermined pressure while in contact with the electronic/electrical component and heated to bond the electronic/electrical component to the circuit pattern by thermocompression.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62116756A JPS63283033A (en) | 1987-05-15 | 1987-05-15 | Die bonding method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62116756A JPS63283033A (en) | 1987-05-15 | 1987-05-15 | Die bonding method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63283033A true JPS63283033A (en) | 1988-11-18 |
Family
ID=14694963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62116756A Pending JPS63283033A (en) | 1987-05-15 | 1987-05-15 | Die bonding method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63283033A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06132626A (en) * | 1992-10-21 | 1994-05-13 | Nec Corp | Printed circuit board |
-
1987
- 1987-05-15 JP JP62116756A patent/JPS63283033A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06132626A (en) * | 1992-10-21 | 1994-05-13 | Nec Corp | Printed circuit board |
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