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CN111602233B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
CN111602233B
CN111602233B CN201880086522.4A CN201880086522A CN111602233B CN 111602233 B CN111602233 B CN 111602233B CN 201880086522 A CN201880086522 A CN 201880086522A CN 111602233 B CN111602233 B CN 111602233B
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China
Prior art keywords
solder material
material layer
solder
semiconductor device
electrode
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CN201880086522.4A
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Chinese (zh)
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CN111602233A (en
Inventor
中川政雄
桑野亮司
篠竹洋平
西村英树
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Publication of CN111602233A publication Critical patent/CN111602233A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0233—Sheets, foils
    • B23K35/0238—Sheets, foils layered
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B23K35/025—Pastes, creams, slurries
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • H01L2924/1304—Transistor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

The method for manufacturing a semiconductor device of the present invention comprises: an assembly forming step of disposing a solder material 44 between the electrode 24 and the electrode tab 32, wherein the solder material 44 has a structure in which a first solder material layer 41 disposed on the surface of the electrode 24 and containing a flux, a second solder material layer 42 disposed on the surface of the electrode tab 32 and containing a flux, and a third solder material layer 43 disposed between the first solder material layer 41 and the second solder material layer 42 and containing no flux are laminated, and wherein the assembly 50 in which the substrate 10, the semiconductor chip 20, and the leads 30 are disposed is formed in the assembly forming step so that the electrode 24 and the electrode tab 32 are in a facing state with the solder material 44 interposed therebetween; and a bonding step of bonding the electrode 24 and the electrode connecting piece 32 via solder 40. According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device with less reliability degradation can be manufactured, and the bonding process can be prevented from becoming complicated.

Description

半导体装置的制造方法Manufacturing method of semiconductor device

技术领域technical field

本发明涉及一种半导体装置的制造方法。The present invention relates to a method of manufacturing a semiconductor device.

背景技术Background technique

以往，有一种半导体装置的制造方法已被普遍知晓，其用于制造经由焊锡而接合有半导体芯片与引线的半导体装置(参照专利文献1)。Conventionally, there is widely known a method for manufacturing a semiconductor device, which is used to manufacture a semiconductor device in which a semiconductor chip and leads are bonded via solder (see Patent Document 1).

如图9所示，专利文献1中记载的以往的半导体装置900包括：基板910，其具有半导体芯片搭载面912；半导体芯片920，其被搭载于半导体芯片搭载面912上，且具有形成于与半导体芯片搭载面912是相向的面上的集电极922、以及具有形成于与半导体芯片搭载面912相向的面是相反侧的面上的发射极924(电极)及形成于与发射极924分离的位置上的栅电极926；以及引线930，其具有电极连接片932，并且该电极连接片932经由焊锡940而与发射极924相接合。As shown in FIG. 9 , the conventional semiconductor device 900 described in Patent Document 1 includes: a substrate 910 having a semiconductor chip mounting surface 912; a semiconductor chip 920 mounted on the semiconductor chip mounting surface 912 and having a The semiconductor chip mounting surface 912 has a collector electrode 922 on the opposite surface, and an emitter electrode 924 (electrode) formed on the surface opposite to the surface facing the semiconductor chip mounting surface 912 and formed on a surface separated from the emitter electrode 924. The gate electrode 926 at the position; and the lead 930 which has the electrode connection piece 932 , and the electrode connection piece 932 is bonded to the emitter electrode 924 via the solder 940 .

根据以往的半导体装置900，电极连接片932是经由焊锡940而与发射极924相接合，即，由于是仅经由焊锡940(不经由导线等中间构件)来直接连接半导体芯片920与引线930，因此，半导体装置900适于具有较大的电流容量且使用大电流的电子设备(例如电源)。According to the conventional semiconductor device 900, the electrode connection pad 932 is bonded to the emitter 924 via the solder 940, that is, the semiconductor chip 920 and the lead 930 are directly connected only via the solder 940 (without intermediate members such as wires). Therefore, the semiconductor device 900 is suitable for an electronic device (for example, a power supply) that has a large current capacity and uses a large current.

以往的半导体装置900是通过如下制造方法(以往的半导体装置的制造方法)来进行制造的。即，以往的半导体装置的制造方法包含：组装体形成工序，该工序形成配置有基板910、半导体芯片920以及引线930的组装体，使得发射极924与电极连接片932成为夹着焊锡材料的相向状态；以及接合工序，该工序在将焊锡材料熔融后，通过将焊锡材料固化来将发射极924与电极连接片932经由焊锡940进行接合。The conventional semiconductor device 900 is manufactured by the following manufacturing method (conventional semiconductor device manufacturing method). That is, the conventional method of manufacturing a semiconductor device includes an assembly forming step of forming an assembly in which the substrate 910, the semiconductor chip 920, and the leads 930 are disposed so that the emitter 924 and the electrode connection piece 932 are opposed to each other with the solder material interposed therebetween. state; and a joining step of joining the emitter 924 and the electrode connection piece 932 via the solder 940 by solidifying the solder material after melting the solder material.

【先行技术文献】【Prior technical literature】

【专利文献1】特开2010-123686号公报[Patent Document 1] JP-A-2010-123686

【专利文献2】特开2017-199809号公报[Patent Document 2] JP-A-2017-199809

一般来说，众所周知，为了缓和作用于半导体芯片与引线之间的焊锡的应力(例如热应力)，将该焊锡的厚度保持在一定厚度以上是比较有效的方法(参照专利文献2)。In general, it is known that in order to alleviate the stress (for example, thermal stress) acting on the solder between the semiconductor chip and the lead, it is relatively effective to keep the thickness of the solder at a certain thickness or more (see Patent Document 2).

然而，在使用含有助焊剂的焊锡材料(例如糊状的焊锡膏)来作为焊锡材料944的情况下，由于接合工序前的焊锡材料944变得过厚(参照图10(a))，故而在将引线930配置在焊锡材料944上后，焊锡材料944会有可能在压坏后溢出到不希望的位置上，并且制造后的半导体装置的可靠性也有可能会下降(参照图10(b))。However, when using a solder material containing flux (for example, paste-like solder paste) as the solder material 944, since the solder material 944 before the bonding process becomes too thick (see FIG. 10(a)), the When the leads 930 are placed on the solder material 944, the solder material 944 may overflow to an undesired position after being crushed, and the reliability of the manufactured semiconductor device may also decrease (see FIG. 10(b)) .

另一方面，在使用不含助焊剂的焊锡材料(粒状焊锡)来作为焊锡材料944的情况下，由于无法通过助焊剂来去除焊锡材料表面的氧化物，故而为了防止焊锡与半导体芯片之间的接合强度、及焊锡与引线之间的接合强度变低，就必须在特殊的条件(在氢气氛下等)下实施接合工序，因此接合工序就会变得繁杂。On the other hand, in the case of using a solder material (granular solder) that does not contain flux as the solder material 944, since the oxides on the surface of the solder material cannot be removed by the flux, in order to prevent friction between the solder and the semiconductor chip, Since the bonding strength and the bonding strength between the solder and the lead wire are lowered, the bonding process must be performed under special conditions (such as under a hydrogen atmosphere), and thus the bonding process becomes complicated.

所以，本发明为了解决上述问题，目的是提供一种半导体装置的制造方法，该制造方法能够制造可靠性不易下降的半导体装置，并且还能够防止接合工序变得繁杂。Therefore, an object of the present invention to solve the above-mentioned problems is to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device whose reliability is less likely to be lowered and also capable of preventing the bonding process from becoming complicated.

发明内容Contents of the invention

【1】本发明的半导体装置的制造方法所制造的半导体装置具备：基板，其具有半导体芯片搭载面；半导体芯片，其被搭载于所述半导体芯片搭载面上，且具有形成在与所述半导体芯片搭载面相向的面是相反侧的面上的电极；以及引线，其具有电极连接片，并且所述电极连接片经由焊锡而与所述电极相接合，所述半导体装置的制造方法，其特征在于，包括：组装体形成工序，在所述电极与所述电极连接片之间配置焊锡材料，所述焊锡材料具有被配置于所述电极的表面且含有助焊剂的第一焊锡材料层、被配置于所述电极连接片的表面且含有助焊剂的第二焊锡材料层、以及被配置于所述第一焊锡材料层与所述第二焊锡材料层之间的且不含有助焊剂的第三焊锡材料层相叠层后的构造，并且，所述组装体形成工序形成配置有所述基板、所述半导体芯片以及所述引线的组装体，使得所述电极与所述电极连接片成为夹着所述焊锡材料的相向状态；以及接合工序，在将所述焊锡材料熔融后，通过将所述焊锡材料固化来将所述电极与所述电极连接片经由所述焊锡进行接合。[1] The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention includes: a substrate having a semiconductor chip mounting surface; The surface facing the chip mounting surface is an electrode on the opposite side; and a lead having an electrode connection piece, and the electrode connection piece is bonded to the electrode via solder, and the method for manufacturing a semiconductor device is characterized in that It includes: an assembly forming step of disposing a solder material between the electrode and the electrode connection piece, the solder material having a first solder material layer disposed on the surface of the electrode and containing flux, being The second solder material layer that is disposed on the surface of the electrode connection piece and contains flux, and the third solder material layer that is disposed between the first solder material layer and the second solder material layer and does not contain flux. In addition, the assembly forming step forms an assembly in which the substrate, the semiconductor chip, and the leads are arranged such that the electrodes and the electrode connection pieces are sandwiched between the solder material layers. The facing state of the solder material; and a joining step of joining the electrode and the electrode connection piece via the solder by solidifying the solder material after melting the solder material.

此外，在本说明书中，“焊锡材料”是指：在通过接合工序来接合对象物之前的焊锡。In addition, in this specification, "solder material" means the solder before objects are joined by a joining process.

【2】在本发明的半导体装置的制造方法中，最好是：所述第一焊锡材料层及所述第二焊锡材料层均由糊状的焊锡材料构成，而所述第三焊锡材料层则由固体状的焊锡材料构成。[2] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that both the first solder material layer and the second solder material layer are made of pasty solder material, and the third solder material layer It consists of a solid solder material.

【3】在本发明的半导体装置的制造方法中，最好是：在所述组装体形成工序中，所述第三焊锡材料层的厚度在所述焊锡材料厚度的60％～90％的范围内。[3] In the method for manufacturing a semiconductor device according to the present invention, preferably, in the assembly forming step, the thickness of the third solder material layer is in the range of 60% to 90% of the thickness of the solder material. Inside.

【4】在本发明的半导体装置的制造方法中，最好是：在所述组装体形成工序中，所述第三焊锡材料层的组成与除去助焊剂成分的所述第一焊锡材料层的组成或除去助焊剂成分的所述第二焊锡材料层的组成相同。[4] In the method of manufacturing a semiconductor device according to the present invention, preferably, in the assembly forming step, the composition of the third solder material layer is the same as that of the first solder material layer except for flux components. The composition of the second solder material layer excluding flux components is the same.

【5】在本发明的半导体装置的制造方法中，最好是：在所述组装体形成工序中，将所述第一焊锡材料层及所述第三焊锡材料层配置在所述第二电极上，并且在将第二焊锡材料层配置在所述电极连接片上后，将所述第三焊锡材料层与所述第二焊锡材料层重叠来形成所述组装体。[5] In the method of manufacturing a semiconductor device according to the present invention, preferably, in the assembly forming step, the first solder material layer and the third solder material layer are arranged on the second electrode. and after disposing the second solder material layer on the electrode connection sheet, the third solder material layer is overlapped with the second solder material layer to form the assembly.

【6】在本发明的半导体装置的制造方法中，最好是：在所述组装体形成工序中，在所述半导体芯片上按照所述第一焊锡材料层、所述第三焊锡材料层及所述第二焊锡材料层的顺序来进行配置后，将所述第二焊锡材料层与所述引线的所述电极连接片重叠来形成所述组装体。[6] In the method of manufacturing a semiconductor device according to the present invention, preferably, in the assembly forming step, the first solder material layer, the third solder material layer, and the After the second solder material layer is arranged sequentially, the second solder material layer is overlapped with the electrode connection piece of the lead to form the assembly.

【7】在本发明的半导体装置的制造方法中，最好是：所述焊锡的厚度大于等于300μm。[7] In the method of manufacturing a semiconductor device of the present invention, it is preferable that the thickness of the solder is equal to or greater than 300 μm.

【8】在本发明的半导体装置的制造方法中，最好是：在所述组装体形成工序中，使用分配器来配置所述第一焊锡材料层及所述第二焊锡材料层。[8] In the method of manufacturing a semiconductor device according to the present invention, preferably, in the assembly forming step, the first solder material layer and the second solder material layer are arranged using a dispenser.

发明效果Invention effect

在本发明的半导体装置的制造方法中，组装体形成工序在电极与电极连接片之间配置焊锡材料，所述焊锡材料具有被配置于第一焊锡材料层与第二焊锡材料层之间的且不含有助焊剂的第三焊锡材料层。通过采用这种方法，在不含有助焊剂的第三焊锡材料层中，由于助焊剂不会在接合工序时(回流时)蒸发，并且第三焊锡材料层部分的厚度也不会因助焊剂的蒸发而导致在接合工序后变薄，因此，就可以无需使接合工序前的(第一～第三焊锡材料层整体的)焊锡材料的厚度变得过厚(比接合工序后的焊锡的厚度稍厚即可)。所以，即使是将引线配置在焊锡材料上也不易压坏焊锡材料，从而就能够防止焊锡材料溢出到不希望的位置上。这样一来，就能够制造可靠性不易下降的半导体装置。In the method of manufacturing a semiconductor device according to the present invention, in the assembly forming step, a solder material is disposed between the electrode and the electrode connection sheet, and the solder material has a solder material disposed between the first solder material layer and the second solder material layer. A third layer of solder material that does not contain flux. By adopting this method, in the third solder material layer that does not contain flux, since the flux does not evaporate during the bonding process (at the time of reflow), and the thickness of the third solder material layer portion is not affected by the flux. Evaporation causes thinning after the joining process, so it is not necessary to make the thickness of the solder material (of the first to third solder material layers as a whole) before the joining process too thick (slightly thicker than the thickness of the solder after the joining process). thick enough). Therefore, even if the lead wire is arranged on the solder material, the solder material is less likely to be crushed, and it is possible to prevent the solder material from overflowing to an undesired position. In this way, it is possible to manufacture a semiconductor device whose reliability is less likely to be lowered.

此外，根据本发明的半导体装置的制造方法，由于组装体形成工序在电极与电极连接片之间配置焊锡材料，所述焊锡材料具有被配置于第一焊锡材料层与第二焊锡材料层之间的且不含有助焊剂的第三焊锡材料层，因此就能够制造将焊锡的厚度保持在一定厚度以上的半导体装置。因此，就能够缓和作用于半导体芯片与引线之间的焊锡的应力(例如热应力)，并且在该观点下，也能够制造可靠性不易下降的半导体装置。In addition, according to the manufacturing method of the semiconductor device of the present invention, due to the assembly forming step, the solder material is disposed between the electrodes and the electrode connection pads, and the solder material has Therefore, it is possible to manufacture a semiconductor device in which the thickness of the solder is maintained at a certain thickness or more. Therefore, the stress (for example, thermal stress) acting on the solder between the semiconductor chip and the lead can be alleviated, and from this point of view, it is also possible to manufacture a semiconductor device whose reliability is less likely to be lowered.

根据本发明的半导体装置的制造方法，由于组装体形成工序在电极与电极连接片之间配置焊锡材料，所述焊锡材料具有被配置于电极的表面且含有助焊剂的第一焊锡材料层、以及被配置于引线的电极连接片的表面且含有助焊剂的第二焊锡材料层，因此就能够通过助焊剂在去除电极、电极连接片以及第三焊锡材料层的表面的掺杂物后的状态下进行接合，从而就能够制造焊锡与半导体芯片或引线之间的密合强度较高的半导体装置。所以，就无需为了防止焊锡与半导体芯片之间的接合强度或焊锡与引线之间的接合强度变得低下而要在特殊的条件(在氢气氛下等)下实施接合工序，从而就能够防止接合工序变得繁杂。According to the manufacturing method of the semiconductor device of the present invention, the solder material having the first solder material layer that is disposed on the surface of the electrode and contains flux, is disposed between the electrode and the electrode connection piece in the assembly forming step, and The second solder material layer, which is arranged on the surface of the electrode connecting piece of the lead and contains flux, can pass through the flux in the state after removing the dopant on the surface of the electrode, the electrode connecting piece, and the third solder material layer. By bonding, it is possible to manufacture a semiconductor device having high adhesion strength between the solder and the semiconductor chip or the lead. Therefore, it is not necessary to carry out the bonding process under special conditions (under a hydrogen atmosphere, etc.) in order to prevent the bonding strength between the solder and the semiconductor chip or the bonding strength between the solder and the lead from becoming low, so that the bonding can be prevented. The process becomes complicated.

附图说明Description of drawings

图1是展示实施方式一涉及的半导体装置1的图。其中,图1(a)是半导体装置1的平面图,图1(b)是图1(a)中的A-A截面图,图1(c)是半导体装置1的主要部分放大截面图。此外,在图1(c)中为了便于说明而省略树脂80的图示。FIG. 1 is a diagram showing a semiconductor device 1 according to the first embodiment. 1(a) is a plan view of the semiconductor device 1, FIG. 1(b) is a cross-sectional view along A-A in FIG. 1(a), and FIG. 1(c) is an enlarged cross-sectional view of the main part of the semiconductor device 1. In addition, in FIG.1(c), illustration of the resin 80 is abbreviate|omitted for convenience of description.

图2是实施方式一涉及的半导体装置的制造方法的流程图。2 is a flowchart of the method of manufacturing the semiconductor device according to the first embodiment.

图3是实施方式一涉及的半导体装置的制造方法的工序图。其中,图3(a)是展示基板准备工序的图,图3(b)是展示半导体芯片搭载工序的图。3 is a process diagram of the method of manufacturing the semiconductor device according to the first embodiment. Among them, FIG. 3( a ) is a diagram showing a substrate preparation process, and FIG. 3( b ) is a diagram showing a semiconductor chip mounting process.

图4是实施方式一涉及的半导体装置的制造方法的工序图。其中,图4(a)是展示第一焊锡材料层配置工序的图，图4(b)是展示第二焊锡材料层配置工序以及第三焊锡材料层配置工序的图。4 is a process diagram of the method of manufacturing the semiconductor device according to the first embodiment. Among them, FIG. 4( a ) is a diagram showing the first solder material layer disposition process, and FIG. 4( b ) is a diagram showing the second solder material layer disposition process and the third solder material layer disposition process.

图5是实施方式一涉及的半导体装置的制造方法的工序图。其中,图5(a)是展示引线框配置工序的图，图5(b)是展示接合工序(回流工序)的图，图5(c)是展示导线接合工序的图。5 is a process diagram of the method of manufacturing the semiconductor device according to the first embodiment. Among them, FIG. 5( a ) is a diagram showing a lead frame arrangement process, FIG. 5( b ) is a diagram showing a bonding process (reflow process), and FIG. 5( c ) is a diagram showing a wire bonding process.

图6是实施方式二涉及的半导体装置的制造方法的工序图。其中,图6(a)是展示第一焊锡材料层配置工序的图，图6(b)是展示第二焊锡材料层配置工序以及第三焊锡材料层配置工序的图，图6(c)是展示引线框配置工序的图。6 is a process diagram of a method of manufacturing a semiconductor device according to Embodiment 2. FIG. Wherein, Fig. 6 (a) is the figure showing the first solder material layer disposition process, Fig. 6 (b) is the figure showing the second solder material layer disposition process and the 3rd solder material layer disposition process, Fig. 6 (c) is A diagram showing the lead frame placement process.

图7是变形例一涉及的半导体装置的制造方法的工序图。其中,图7(a)是展示半导体芯片配置工序的图，图7(b)是展示第一焊锡材料层配置工序、第二焊锡材料层配置工序以及第三焊锡材料层配置工序的图，图7(c)是展示引线框配置工序的图。7 is a process diagram of a method of manufacturing a semiconductor device according to Modification 1. FIG. Wherein, Fig. 7 (a) is the figure showing the semiconductor chip disposition process, Fig. 7 (b) is the figure showing the first solder material layer disposition process, the second solder material layer disposition process and the 3rd solder material layer disposition process, Fig. 7(c) is a figure showing the lead frame arrangement process.

图8是展示变形例二涉及的半导体装置2的图。其中，图8(a)是半导体装置2的立体图，图8(b)是图8(a)中的B-B截面图。在图8中，符号10a、10b表示基板，12a、12b表示半导体芯片搭载面，14a、14b表示绝缘性基板，18a、18b表示散热用金属板，40a、40b表示焊锡。FIG. 8 is a diagram showing a semiconductor device 2 according to Modification 2. As shown in FIG. Among them, FIG. 8( a ) is a perspective view of the semiconductor device 2 , and FIG. 8( b ) is a B-B sectional view in FIG. 8( a ). In FIG. 8, reference numerals 10a and 10b denote substrates, 12a and 12b denote semiconductor chip mounting surfaces, 14a and 14b denote insulating substrates, 18a and 18b denote metal plates for heat dissipation, and 40a and 40b denote solder.

图9是展示以往的半导体装置900的截面图。在图9中，符号946表示焊锡，符号960、962表示端子，符号970表示导线，符号980表示树脂。FIG. 9 is a cross-sectional view showing a conventional semiconductor device 900 . In FIG. 9 , symbol 946 denotes solder, symbols 960 and 962 denote terminals, symbol 970 denotes lead wires, and symbol 980 denotes resin.

图10是展示以往的半导体装置的制造方法的问题点的图。其中，图10(a)是展示引线配置前的组装体的情况的图，图10(b)是展示引线配置后的组装体的情况的图。符号944、945表示焊锡材料(糊状的焊锡材料)。FIG. 10 is a diagram illustrating problems of a conventional method of manufacturing a semiconductor device. Among them, FIG. 10( a ) is a diagram showing the state of the assembly before the wires are arranged, and FIG. 10( b ) is a diagram showing the state of the assembly after the wires are arranged. Symbols 944 and 945 represent solder materials (paste solder materials).

具体实施方式Detailed ways

以下，将根据图示的实施方式来说明本发明的半导体装置的制造方法。其中，各附图只是模式图，不一定严格反映出实际的尺寸大小。Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described based on the illustrated embodiments. In addition, each drawing is only a schematic diagram, and does not necessarily reflect the actual size strictly.

【实施方式一】【Implementation Mode 1】

1.实施方式涉及的半导体装置1的构成1. Configuration of the semiconductor device 1 according to the embodiment

实施方式一涉及的半导体装置1为了缓和作用于半导体芯片与引线之间的焊锡的应力(例如热应力)，其焊锡的厚度被保持在一定厚度以上。如图1所示，实施方式涉及的半导体装置1包括：基板10；半导体芯片20；引线30、62、64；焊锡40、46；以及导线70，其中，除了引线30、62、64的外部连接端子以及散热性的金属板18的一部分以外，其余部件都被树脂80进行树脂封装。In the semiconductor device 1 according to Embodiment 1, the thickness of the solder is kept at a certain thickness or more in order to alleviate stress (for example, thermal stress) acting on the solder between the semiconductor chip and the lead. As shown in FIG. 1 , a semiconductor device 1 according to the embodiment includes: a substrate 10; a semiconductor chip 20; leads 30, 62, 64; solder 40, 46; The components other than the terminals and a part of the heat-dissipating metal plate 18 are resin-sealed with the resin 80 .

基板10是具有半导体芯片搭载面12的基板。虽然能够使用适当的基板(例如印刷基板)来作为基板10，但是在实施方式一中使用的是DCB(Direct Cоpper Bonding)基板，该DCB基板具有：绝缘性基板14；被形成在绝缘性基板14的一面且具有半导体芯片搭载面12的电路16；以及被形成在绝缘性基板14的另一面的散热用金属板18。其中，散热用金属板18从树脂80露出。The substrate 10 is a substrate having a semiconductor chip mounting surface 12 . Although an appropriate substrate (such as a printed circuit board) can be used as the substrate 10, in the first embodiment, a DCB (Direct Copper Bonding) substrate is used. The DCB substrate has: an insulating substrate 14; A circuit 16 having a semiconductor chip mounting surface 12 on one side; and a heat dissipation metal plate 18 formed on the other side of the insulating substrate 14 . Among them, the metal plate 18 for heat dissipation is exposed from the resin 80 .

半导体芯片20是IGBT(Insulated Gate Bipolar Transistor)，其具有：形成在一个面(与半导体芯片搭载面12相向的面)上的集电极22、形成在另一个面(与半导体芯片搭载面12相向的面是相反侧的面)上的发射极24、以及形成在与发射极24分离的位置上的栅电极26。The semiconductor chip 20 is an IGBT (Insulated Gate Bipolar Transistor), which has a collector electrode 22 formed on one surface (the surface facing the semiconductor chip mounting surface 12), and a collector electrode 22 formed on the other surface (the surface facing the semiconductor chip mounting surface 12). The emitter electrode 24 on the opposite side), and the gate electrode 26 formed at a position separated from the emitter electrode 24 .

集电极22经由焊锡46而与基板10的半导体芯片搭载面12相接合，并且集电极22经由焊锡46、基板10(电路16)以及引线64而与外部相连接。Collector 22 is joined to semiconductor chip mounting surface 12 of substrate 10 via solder 46 , and collector 22 is connected to the outside via solder 46 , substrate 10 (circuit 16 ), and lead 64 .

发射极24经由焊锡40而与引线30的电极连接片32相接合，并且发射极24经由焊锡40以及引线30(外部连接端子34)而与外部相连接。The emitter 24 is bonded to the electrode connection piece 32 of the lead 30 via solder 40 , and the emitter 24 is connected to the outside via the solder 40 and the lead 30 (external connection terminal 34 ).

引线30、62、64是平板状的金属构件，其是通过将引线框分开后形成的。引线30、62、64的截面积更大于导线，并且能够流通大电流。The leads 30 , 62 , and 64 are flat metal members formed by dividing a lead frame. The lead wires 30, 62, 64 have a larger cross-sectional area than the wires and are capable of passing large currents.

在引线30的一端部上具有用于与发射极24连接的电极连接片32，在引线30的另一端部上具有用于与外部连接的外部连接端子34。One end of the lead 30 has an electrode connection piece 32 for connecting to the emitter 24 , and the other end of the lead 30 has an external connection terminal 34 for connecting to the outside.

引线62的一端部经由导线70而与栅电极26相连接，引线62的另一端部为外部连接用端子。One end of the lead 62 is connected to the gate electrode 26 via a wire 70 , and the other end of the lead 62 is a terminal for external connection.

引线64的一端部与电路16相连接，而该电路16连接着集电极22，引线64的另一端部为外部连接用端子。One end of the lead wire 64 is connected to the circuit 16 connected to the collector electrode 22 , and the other end of the lead wire 64 is a terminal for external connection.

焊锡40、46为具有导电性及粘着性的合金或金属。焊锡40、46是通过将焊锡材料加热来熔融后固化而成。The solders 40 and 46 are alloys or metals having electrical conductivity and adhesiveness. The solders 40 and 46 are formed by heating a solder material to melt and then solidify.

焊锡40接合发射极24与电极连接片32。焊锡40的厚度(焊锡厚度)比焊锡46(基板10与半导体芯片20之间的焊锡)的厚度更厚，其厚度例如是大于等于300μm、或为500μm。关于焊锡40的形成方法会进行后述。The solder 40 joins the emitter 24 and the electrode connection pad 32 . The thickness of the solder 40 (solder thickness) is thicker than the thickness of the solder 46 (solder between the substrate 10 and the semiconductor chip 20 ), and its thickness is, for example, 300 μm or more, or 500 μm. The method of forming the solder 40 will be described later.

焊锡46接合集电极22与半导体芯片搭载面12。焊锡40由含有助焊剂的糊状焊锡材料(例如，所说的焊锡膏)构成，并且其被通过印刷而配置在基板10的半导体芯片搭载面12上，在回流后通过加热来接合基板10与半导体芯片20。此外，在位于半导体芯片20与引线30之间的焊锡40中存在着要缓和作用于焊锡的应力(例如热应力)的情况，而在位于基板10与半导体芯片20之间的焊锡46中则不存在这样的情况，并且如果厚度变厚，导通损耗也会变大，因此位于基板10与半导体芯片20之间的焊锡46与位于半导体芯片20与引线30之间的焊锡40不同，其理想的厚度最好是较薄(将焊锡的厚度设为一定厚度以下)。The solder 46 joins the collector electrode 22 and the semiconductor chip mounting surface 12 . The solder 40 is composed of a paste solder material (for example, so-called solder paste) containing flux, and it is arranged on the semiconductor chip mounting surface 12 of the substrate 10 by printing, and the substrate 10 and the substrate 10 are joined by heating after reflow. semiconductor chip 20 . In addition, in the solder 40 located between the semiconductor chip 20 and the lead 30, there is a case where the stress (such as thermal stress) acting on the solder is relaxed, but in the solder 46 located between the substrate 10 and the semiconductor chip 20, there is no case. There is such a situation, and if the thickness becomes thicker, the conduction loss will also become larger, so the solder 46 between the substrate 10 and the semiconductor chip 20 is different from the solder 40 between the semiconductor chip 20 and the lead 30, and its ideal The thickness is preferably thin (the thickness of the solder should be less than a certain thickness).

树脂80能够使用合适的树脂。Suitable resin can be used for the resin 80 .

在上述实施方式一涉及的半导体装置1中，为了缓和作用于半导体芯片20与引线30之间的焊锡40的应力(例如热应力)，将半导体芯片20与引线30之间的焊锡40的厚度保持在一定厚度以上。In the semiconductor device 1 according to the above-mentioned first embodiment, in order to relax the stress (such as thermal stress) acting on the solder 40 between the semiconductor chip 20 and the lead 30, the thickness of the solder 40 between the semiconductor chip 20 and the lead 30 is kept above a certain thickness.

一般来说，为了接合半导体芯片与引线之间，虽然是使用能够去除接合面上的掺杂物(氧化物等)的含有助焊剂的焊锡材料(例如，所说的焊锡膏)，但是由于含有助焊剂的焊锡材料会因助焊剂在接合工序时(回流时)蒸发而导致焊锡的厚度变薄，因此如果将其用于上述实施方式一涉及的半导体装置1的制造，就必须充分加厚接合工序前(回流前)的焊锡材料的厚度。Generally, in order to bond semiconductor chips and leads, solder materials containing flux (for example, the so-called solder paste) that can remove impurities (oxides, etc.) on the bonding surface are used. The solder material of the flux will cause the thickness of the solder to become thin due to the evaporation of the flux during the bonding process (during reflow). Therefore, if it is used in the manufacture of the semiconductor device 1 according to the above-mentioned first embodiment, it is necessary to sufficiently thicken the bonding material. The thickness of the solder material before the process (before reflow).

但是，在充分加厚焊锡材料的厚度后，在接合工序前(回流前)将引线配置在焊锡材料上时，焊锡材料会有可能在压坏后溢出到不希望的位置上。However, when the thickness of the solder material is sufficiently thickened and the leads are placed on the solder material before the bonding process (before reflow), the solder material may protrude to an undesired position after being crushed.

因此，在本发明中使用了下述的实施方式一涉及的半导体装置的制造方法，该制造方法能够将接合工序后(回流后)的焊锡的厚度保持在一定厚度以上，并且接合工序前(回流前)的焊锡材料的厚度不会变得过厚。Therefore, in the present invention, the semiconductor device manufacturing method according to Embodiment 1 that can keep the thickness of the solder after the bonding process (after reflow) at a certain thickness or more and that can maintain the thickness of the solder before the bonding process (after reflow) is used in the present invention. Before) the thickness of the solder material will not become too thick.

2.实施方式一涉及的半导体装置的制造方法2. Manufacturing method of semiconductor device according to Embodiment 1

如图2所示，实施方式一涉及的半导体装置的制造方法包含：基板准备工序S100；组装体形成工序S200；接合工序S300；导线接合工序S400；树脂封装工序S500；以及引线加工工序S600。As shown in FIG. 2 , the method of manufacturing a semiconductor device according to Embodiment 1 includes: a substrate preparation step S100 ; an assembly forming step S200 ; a bonding step S300 ; a wire bonding step S400 ; a resin sealing step S500 ;

(1)基板准备工序S100(1) Substrate preparation process S100

在基板准备工序S100中，准备基板10(参照图3(a))。具体来说，在规定的夹具上定位并配置基板10。In the substrate preparation step S100 , the substrate 10 is prepared (see FIG. 3( a )). Specifically, the substrate 10 is positioned and arranged on a predetermined jig.

(2)组装体形成工序S200(2) Assembly forming step S200

在组装体形成工序S200中，形成配置有基板10、半导体芯片20以及引线30的组装体50(参照图5(a))，使得基板10的半导体芯片搭载面12与半导体芯片的集电极22成为夹着焊锡材料45的相向状态，并且半导体芯片20的发射极24与引线30的电极连接片32成为夹着焊锡材料44(参照图5(a))的相向状态。组装体形成工序S200包含：半导体芯片搭载工序S210；第一焊锡材料层配置工序S220；第三焊锡材料层配置工序S230；第二焊锡材料层配置工序S240；以及引线框配置工序S250。In the assembly forming step S200, an assembly 50 (see FIG. 5(a)) in which the substrate 10, the semiconductor chip 20, and the leads 30 are arranged is formed such that the semiconductor chip mounting surface 12 of the substrate 10 and the collector electrode 22 of the semiconductor chip become The emitter 24 of the semiconductor chip 20 and the electrode connection piece 32 of the lead 30 are facing each other with the solder material 45 sandwiched therebetween (see FIG. 5( a )). Assembly forming process S200 includes: semiconductor chip mounting process S210; first solder material layer disposing process S220; third solder material layer disposing process S230; second solder material layer disposing process S240; and lead frame disposing process S250.

(2-1)半导体芯片搭载工序S210(2-1) Semiconductor chip mounting process S210

在半导体芯片搭载工序S210中，在基板10的半导体芯片搭载面12上经由焊锡材料45来搭载半导体芯片20(参照图3(b))。具体来说，首先在基板10的半导体芯片搭载面12上印刷糊状的焊锡材料45(例如，所说的焊锡膏)。随后，在半导体芯片搭载面12上搭载半导体芯片20，使得半导体芯片搭载面12与半导体芯片20的集电极22成为夹着焊锡材料45的相向状态。In the semiconductor chip mounting step S210 , the semiconductor chip 20 is mounted on the semiconductor chip mounting surface 12 of the substrate 10 via the solder material 45 (see FIG. 3( b )). Specifically, first, paste-like solder material 45 (for example, so-called solder paste) is printed on the semiconductor chip mounting surface 12 of the substrate 10 . Subsequently, the semiconductor chip 20 is mounted on the semiconductor chip mounting surface 12 such that the semiconductor chip mounting surface 12 and the collector electrode 22 of the semiconductor chip 20 are in an opposing state with the solder material 45 interposed therebetween.

此外，在实施方式一中，虽然是对焊锡材料45进行印刷，但是也可以是以通过分配器来提供焊锡材料、通过由焊锡供给器等送出的焊锡丝来提供焊锡材料、通过流入熔融后的焊锡材料来提供焊锡材料等适当的方法来提供焊锡材料。In addition, in the first embodiment, although the solder material 45 is printed, the solder material may be supplied from a dispenser, supplied from a solder wire sent out from a solder feeder, etc. Solder material to provide solder material and other appropriate methods to provide solder material.

焊锡膏是在焊锡粉中添加助焊剂后构成的具有适当的粘度的糊状。助焊剂是在高温下挥发的成分。作为助焊剂，使用以松香、改性松香、合成树脂等为主要成分的树脂系助焊剂，有时也会有进一步添加触变剂、活性剂以及活性剂用溶剂、分散稳定剂等的情况。Solder paste is a paste with appropriate viscosity formed by adding flux to solder powder. Flux is a component that evaporates at high temperatures. As the flux, resin-based flux mainly composed of rosin, modified rosin, synthetic resin, etc. is used, and a thixotropic agent, activator, solvent for activator, dispersion stabilizer, etc. may be further added.

(2-2)第一焊锡材料层配置工序S220(2-2) First solder material layer arrangement step S220

在第一焊锡材料层配置工序S220中，在半导体芯片20的发射极24上配置由含有助焊剂的糊状的焊锡材料所构成的第一焊锡材料层41(参照图4(a))。第一焊锡材料层配置工序S220例如通过分配器D来将含有助焊剂的糊状的焊锡材料(例如，所说的焊锡膏)提供至发射极24上，并以此来配置第一焊锡材料层41。第一焊锡材料层41的厚度只要是能够充分接合第三焊锡材料层43与发射极24的厚度即可。In the first solder material layer arranging step S220 , the first solder material layer 41 made of paste solder material containing flux is placed on the emitter 24 of the semiconductor chip 20 (see FIG. 4( a )). The first solder material layer configuration process S220, for example, provides a pasty solder material containing flux (for example, the so-called solder paste) on the emitter 24 through the dispenser D, and thereby configures the first solder material layer. 41. The thickness of the 1st solder material layer 41 should just be the thickness which can fully join the 3rd solder material layer 43 and the emitter electrode 24.

此外，虽然有想到各种方法来作为提供糊状的焊锡材料的方法，但是由于在将糊状的焊锡材料提供至发射极24上时需要焊锡量的细微调整及供给部位的准确性，因此最好是通过分配器来提供糊状的焊锡材料。In addition, various methods have been conceived as a method of supplying the paste-like solder material, but since fine adjustment of the amount of solder and accuracy of the supply position are required when supplying the paste-like solder material to the emitter 24, it is most preferable It is best to provide pasty solder material through a dispenser.

(2-3)第三焊锡材料层配置工序S230(2-3) The third solder material layer arrangement step S230

在第三焊锡材料层配置工序S230中，将第三焊锡材料层43配置于第一焊锡材料层41上(参照图4(b)下侧)。In the third solder material layer arrangement step S230 , the third solder material layer 43 is arranged on the first solder material layer 41 (see FIG. 4( b ) lower side).

第三焊锡材料层43是由不含有助焊剂的固体状的焊锡材料构成的板状或膜状的焊锡材料(所说的焊锡板)。第三焊锡材料层43的厚度在焊锡材料44(参照图5(a))的厚度的大约60％～90％的范围内。此外，第三焊锡材料层43的厚度在焊锡40(回流后的焊锡厚度)的大约75％～95％的范围内。第三焊锡材料层43的厚度是第一焊锡材料层41的至少数倍。在实施方式一中，虽然第三焊锡材料层43的组成(主成分)与除去助焊剂成分的第一焊锡材料层41的组成及除去助焊剂成分的第二焊锡材料层42的组成(主成分)相同，但是第三焊锡材料层43的组成(主成分)也可以是仅与其中的一方相同或不相同。The third solder material layer 43 is a plate-like or film-like solder material (so-called solder plate) made of a solid solder material that does not contain flux. The thickness of the third solder material layer 43 is in the range of approximately 60% to 90% of the thickness of the solder material 44 (see FIG. 5( a )). In addition, the thickness of the third solder material layer 43 is in the range of about 75%˜95% of the solder 40 (solder thickness after reflow). The thickness of the third solder material layer 43 is at least several times that of the first solder material layer 41 . In Embodiment 1, although the composition (main component) of the third solder material layer 43 is the same as that of the first solder material layer 41 except the flux component and the composition (main component) of the second solder material layer 42 except the flux component ) are the same, but the composition (main component) of the third solder material layer 43 may be the same as or different from only one of them.

(2-4)第二焊锡材料层配置工序S240(2-4) Second solder material layer arrangement step S240

在第二焊锡材料层配置工序S240中，在引线30的电极连接片32上配置由具有助焊剂的糊状的焊锡材料所构成的第二焊锡材料层42(参照图4(b)上侧)。具体来说，在构成引线30、62、64的引线框中的成为引线30部分处的电极连接片32的表面上，例如通过分配器来提供含有助焊剂的糊状焊锡材料(例如，所说的焊锡膏)并配置第二焊锡材料层42。第二焊锡材料层42的厚度与第一焊锡材料层41的厚度相同，其厚度只要能够充分接合第三焊锡材料层43与电极连接片32即可。此外，可以在引线框配置工序S250之前的任意阶段实施第二焊锡材料层配置工序S240。In the second solder material layer arrangement step S240, the second solder material layer 42 made of paste solder material with flux is placed on the electrode connection piece 32 of the lead 30 (see the upper side of FIG. 4( b )). . Specifically, on the surface of the electrode connection sheet 32 that becomes the part of the lead 30 in the lead frame constituting the lead 30, 62, 64, for example, a paste solder material containing flux (for example, said solder paste) and configure the second solder material layer 42. The thickness of the second solder material layer 42 is the same as that of the first solder material layer 41 , as long as the thickness can sufficiently bond the third solder material layer 43 and the electrode connection piece 32 . In addition, the second solder material layer arrangement step S240 may be performed at any stage before the lead frame arrangement step S250.

(2-5)引线框配置工序S250(2-5) Lead frame placement process S250

在引线框配置工序S250中，在配置于半导体芯片20上的第三焊锡材料层43上以使引线30上的第二焊锡材料层42与第三焊锡材料层重叠的方式来配置引线30(引线框)(参照图5(a))。这时，引线框内的引线62、64也被配置于规定的位置。从而在发射极24与电极连接片32之间配置焊锡材料44，该焊锡材料44具有被配置于集电极22的表面且含有助焊剂的第一焊锡材料层41、被配置于引线30中的电极连接片32的表面且含有助焊剂的第二焊锡材料层42、以及被配置于第一焊锡材料层41与第二焊锡材料层42之间的且不含有助焊剂的第三焊锡材料层43相叠层后的构造。In the lead frame arranging step S250, the lead 30 is arranged on the third solder material layer 43 arranged on the semiconductor chip 20 so that the second solder material layer 42 on the lead 30 overlaps with the third solder material layer (lead 30 ). frame) (see Figure 5(a)). At this time, the leads 62 and 64 in the lead frame are also arranged at predetermined positions. Thus, a solder material 44 is arranged between the emitter electrode 24 and the electrode connection piece 32. The solder material 44 has a first solder material layer 41 arranged on the surface of the collector electrode 22 and containing flux, and an electrode arranged in the lead 30. The second solder material layer 42 containing flux on the surface of the connecting sheet 32 and the third solder material layer 43 that is disposed between the first solder material layer 41 and the second solder material layer 42 and does not contain flux The laminated structure.

由此，就能够在基板10的半导体芯片搭载面12与半导体芯片的发射极24是成为夹着焊锡材料45的相向状态、并且半导体芯片20的集电极与引线30的电极连接片32是成为夹着焊锡材料44的相向状态下，形成配置有基板10、半导体芯片20以及引线30的组装体50。As a result, the semiconductor chip mounting surface 12 of the substrate 10 and the emitter electrode 24 of the semiconductor chip are facing each other with the solder material 45 sandwiched between them, and the collector electrode of the semiconductor chip 20 and the electrode connection piece 32 of the lead wire 30 are sandwiched. In the state where the solder material 44 faces each other, an assembly 50 in which the substrate 10 , the semiconductor chip 20 , and the leads 30 are arranged is formed.

(3)接合工序(回流工序)S300(3) Joining process (reflow process) S300

在接合工序(回流工序)S300中，将组装体50放入回流炉(未图示)进行加热，并在熔融焊锡材料44、45后将焊锡材料44、45固化来形成焊锡40、46(参照图5(b))。因此，在经由焊锡46来接合基板10的半导体芯片搭载面12与半导体芯片20的集电极22的同时，经由焊锡40来接合半导体芯片20的发射极24与引线30的电极连接片32。这时，由于含有助焊剂的第一焊锡材料层41及第二焊锡材料层42处的助焊剂蒸发，因此第一焊锡材料层41及第二焊锡材料层42的厚度会变薄。In the bonding process (reflow process) S300, the assembled body 50 is placed in a reflow furnace (not shown) to be heated, and after melting the solder materials 44 and 45, the solder materials 44 and 45 are solidified to form the solders 40 and 46 (see Figure 5(b)). Therefore, the semiconductor chip mounting surface 12 of the substrate 10 and the collector electrode 22 of the semiconductor chip 20 are bonded via the solder 46 , and the emitter 24 of the semiconductor chip 20 and the electrode connection piece 32 of the lead 30 are bonded via the solder 40 . At this time, since the flux in the first solder material layer 41 and the second solder material layer 42 containing flux evaporates, the thicknesses of the first solder material layer 41 and the second solder material layer 42 become thin.

(4)导线接合工序S400(4) Wire bonding process S400

接着，使用导线70来连接栅电极26与引线(图1中的引线62)(参照图5(c))。导线70可以使用合适的导线。Next, the gate electrode 26 and the lead (lead 62 in FIG. 1 ) are connected using wire 70 (see FIG. 5( c )). A suitable wire can be used for the wire 70 .

(5)树脂封装工序S500以及引线加工工序S600(5) Resin encapsulation process S500 and lead processing process S600

随后，除了引线30、62、64的外部端子及散热用金属板18以外，全部以树脂80来进行树脂封装(树脂封装工序S500，未图示)，接着在从引线框分开引线30、62、64的同时，进行规定部位的折弯等加工(引线加工工序S600，未图示)。Then, except for the external terminals of the leads 30, 62, 64 and the metal plate 18 for heat dissipation, all are resin-encapsulated with the resin 80 (resin encapsulation step S500, not shown), and then the leads 30, 62, At the same time as 64, processing such as bending of a predetermined portion is performed (lead wire processing step S600, not shown).

由此就能够制造实施方式一涉及的半导体装置1。Thus, the semiconductor device 1 according to the first embodiment can be manufactured.

3.实施方式一涉及的半导体装置的制造方法的效果3. Effects of the semiconductor device manufacturing method according to the first embodiment

在施方式一涉及的半导体装置的制造方法中，组装体形成工序在发射极24与电极连接片32之间配置焊锡材料44，所述焊锡材料44具有被配置于第一焊锡材料层41与第二焊锡材料层42之间的且不含有助焊剂的第三焊锡材料层43。通过采用这种方法，在不含有助焊剂的第三焊锡材料层43中，由于助焊剂不会在接合工序时(回流时)蒸发，并且第三焊锡材料层43部分的厚度也不会因助焊剂的蒸发而导致在接合工序后变薄，因此，就可以无需使接合工序前的(第一～第三焊锡材料层整体的)焊锡材料44的厚度变得过厚(比接合工序后的焊锡的厚度稍厚即可)。所以，即使是将引线30(引线框)配置在焊锡材料44上也不易压坏焊锡材料44，从而就能够防止焊锡材料44溢出到不希望的位置上。这样一来，就能够制造可靠性不易下降的半导体装置。In the manufacturing method of the semiconductor device according to the first embodiment, in the assembly forming step, the solder material 44 having the thickness of the first solder material layer 41 and the second solder material layer 41 is placed between the emitter electrode 24 and the electrode connection piece 32 . The third solder material layer 43 between the two solder material layers 42 does not contain flux. By adopting this method, in the third solder material layer 43 that does not contain flux, since the flux will not evaporate during the bonding process (during reflow), and the thickness of the third solder material layer 43 will not be affected by the flux. The evaporation of the flux leads to thinning after the bonding process, so it is not necessary to make the thickness of the solder material 44 (overall the first to third solder material layers) before the bonding process to become too thick (compared to the solder material layer after the bonding process). The thickness is slightly thicker). Therefore, even if the lead wire 30 (lead frame) is arranged on the solder material 44, the solder material 44 is not easily crushed, and the solder material 44 can be prevented from overflowing to an undesired position. In this way, it is possible to manufacture a semiconductor device whose reliability is less likely to be lowered.

此外，根据本发明的半导体装置的制造方法，由于组装体形成工序在发射极24与电极连接片32之间配置焊锡材料44，所述焊锡材料44具有被配置于第一焊锡材料层41与第二焊锡材料层42之间的且不含有助焊剂的第三焊锡材料层43，因此就能够制造将焊锡40的厚度保持在一定厚度以上的半导体装置。因此，就能够缓和作用于半导体芯片20与引线30之间的焊锡40的应力(例如热应力)，并且在该观点下，也能够制造可靠性不易下降的半导体装置。In addition, according to the manufacturing method of the semiconductor device of the present invention, due to the assembly forming step, the solder material 44 is disposed between the emitter electrode 24 and the electrode connection piece 32, and the solder material 44 has The third solder material layer 43 between the two solder material layers 42 does not contain flux, so it is possible to manufacture a semiconductor device in which the thickness of the solder 40 is kept above a certain thickness. Therefore, the stress (for example, thermal stress) acting on the solder 40 between the semiconductor chip 20 and the lead 30 can be alleviated, and from this point of view, a semiconductor device whose reliability is less likely to be lowered can also be manufactured.

根据实施方式一涉及的半导体装置的制造方法，由于组装体形成工序在发射极24与电极连接片32之间配置焊锡材料44，所述焊锡材料44具有被配置于发射极24的表面且含有助焊剂的第一焊锡材料层41、以及被配置于引线30的电极连接片32的表面且含有助焊剂的第二焊锡材料层42，因此就能够通过助焊剂在去除发射极24、电极连接片32以及第三焊锡材料层43的表面的掺杂物后的状态下进行接合，从而就能够制造焊锡40与半导体芯片20或引线30之间的接合强度较高的半导体装置。所以，就无需为了防止焊锡40与半导体芯片20之间的接合强度或焊锡40与引线30之间的接合强度变得低下而要在特殊的条件(在氢气氛下等)下实施接合工序，从而就能够防止接合工序变得繁杂。According to the semiconductor device manufacturing method according to Embodiment 1, the solder material 44 having a surface arranged on the emitter electrode 24 and containing auxiliary The first solder material layer 41 of the flux, and the second solder material layer 42 that is arranged on the surface of the electrode connection piece 32 of the lead 30 and contains flux, so the emitter 24 and the electrode connection piece 32 can be removed by the flux. And the third solder material layer 43 is bonded in a state where the surface of the third solder material layer 43 is doped, so that a semiconductor device with high bonding strength between the solder 40 and the semiconductor chip 20 or the lead 30 can be manufactured. Therefore, it is not necessary to carry out the bonding process under special conditions (under a hydrogen atmosphere, etc.) in order to prevent the bonding strength between the solder 40 and the semiconductor chip 20 or the bonding strength between the solder 40 and the lead 30 from becoming low. It is possible to prevent the bonding process from becoming complicated.

此外，根据实施方式一涉及的半导体装置的制造方法，由于第一焊锡材料层41及第二焊锡材料层42均是由具有适当粘度的糊状的焊锡材料构成，因此就能够将第一焊锡材料层41及第二焊锡材料层42保留在发射极24及电极连接片32上(能够防止因粘性过小而导致焊锡及助焊剂从电极流出)，所以处理就会变得容易。此外，由于焊锡粉与助焊剂被适当地混合，因此就能够将助焊剂均匀地提供至接合面。In addition, according to the manufacturing method of the semiconductor device according to the first embodiment, since both the first solder material layer 41 and the second solder material layer 42 are composed of a pasty solder material having an appropriate viscosity, the first solder material can be The layer 41 and the second solder material layer 42 remain on the emitter 24 and the electrode connection piece 32 (to prevent the solder and flux from flowing out of the electrodes due to too low viscosity), so the handling becomes easy. In addition, since the solder powder and the flux are properly mixed, the flux can be uniformly supplied to the bonding surface.

根据实施方式一涉及的半导体装置的制造方法，由于第三焊锡材料层43是由固体状的焊锡材料所构成，因此即使是将引线30配置在焊锡材料上，第三焊锡材料层43也不易成为压坏的形状，从而就能够准确地防止焊锡溢出到不希望的位置上。According to the method of manufacturing a semiconductor device according to Embodiment 1, since the third solder material layer 43 is composed of a solid solder material, even if the leads 30 are placed on the solder material, the third solder material layer 43 is less likely to become The crushed shape can accurately prevent the solder from overflowing to an undesired position.

此外，根据实施方式一涉及的半导体装置的制造方法，由于在组装体形成工序中，第三焊锡材料层43的厚度在焊锡材料44厚度的60％～90％的范围内，即由于即使是将引线配置在焊锡材料上，焊锡材料44的厚度几乎也不会变化，并且由于焊锡材料不易成为压坏的形状的第三焊锡材料层43的比例较大，因此即使是将引线30配置在焊锡材料44上，也能够更为准确地防止焊锡材料溢出到不希望的位置上。另外，由于第一焊锡材料层41及第二焊锡材料层42的厚度在焊锡材料44的厚度的10％～40％的范围内，因此即使是在焊锡材料44中的含有助焊剂的焊锡材料所占比例较小，并且助焊剂在接合工序时(回流时)蒸发的情况下，对接合工序后的焊锡的厚度所造成的影响也较小。In addition, according to the semiconductor device manufacturing method according to the first embodiment, since the thickness of the third solder material layer 43 is within the range of 60% to 90% of the thickness of the solder material 44 in the assembly forming process, that is, even if the The lead wire is arranged on the solder material, and the thickness of the solder material 44 hardly changes, and since the third solder material layer 43 in which the solder material is not easily crushed is relatively large, even if the lead wire 30 is arranged on the solder material 44, it is also possible to more accurately prevent the solder material from overflowing to an undesired position. In addition, since the thickness of the first solder material layer 41 and the second solder material layer 42 is within the range of 10% to 40% of the thickness of the solder material 44, even if the solder material containing flux in the solder material 44 The proportion is small, and when the flux evaporates during the bonding process (during reflow), the influence on the thickness of the solder after the bonding process is also small.

将第三焊锡材料层43的厚度设为大于等于60％是因为在第三焊锡材料层43的厚度不满焊锡材料44的厚度的60％的情况下，焊锡材料在接合工序中会有容易成为压坏的形状的可能性，而将第三焊锡材料层43的厚度设为不满90％是因为在第三焊锡材料层43的厚度大于等于焊锡材料44的厚度的90％的情况下，第一焊锡材料层41及第二焊锡材料层42的比例会变小，并且通过第一焊锡材料层41及第二焊锡材料层42内的助焊剂来提高接合强度也会变得困难。从该观点来说，第三焊锡材料层43更为理想的厚度是在焊锡材料44的厚度的65％～85％的范围内。The reason why the thickness of the third solder material layer 43 is set to be 60% or more is because if the thickness of the third solder material layer 43 is less than 60% of the thickness of the solder material 44, the solder material may easily become compressed during the bonding process. The reason why the thickness of the third solder material layer 43 is less than 90% is because the thickness of the third solder material layer 43 is greater than or equal to 90% of the thickness of the solder material 44. The ratio of the material layer 41 and the second solder material layer 42 becomes small, and it becomes difficult to improve the joint strength by the flux in the first solder material layer 41 and the second solder material layer 42 . From this point of view, the more desirable thickness of the third solder material layer 43 is within the range of 65% to 85% of the thickness of the solder material 44 .

此外，根据实施方式一涉及的半导体装置的制造方法，由于在组装体形成工序中，第三焊锡材料层43的厚度在焊锡材料44厚度的60％～90％的范围内，并且焊锡材料44厚度中的不含有助焊剂的第三焊锡材料层43的比例较大，因此，即使焊锡材料44在接合工序(回流工序)时被加热，也能够减小因助焊剂被气化而导致的焊锡飞散的可能性。所以，就不易引起因飞散的焊锡所导致的短路或接触不良等问题，从而就能够制造可靠性不易下降的半导体装置。In addition, according to the semiconductor device manufacturing method according to Embodiment 1, since the thickness of the third solder material layer 43 is in the range of 60% to 90% of the thickness of the solder material 44 in the assembly forming process, and the thickness of the solder material 44 is The proportion of the third solder material layer 43 that does not contain flux is large, so even if the solder material 44 is heated during the bonding process (reflow process), it is possible to reduce solder spatter caused by vaporization of the flux. possibility. Therefore, problems such as short circuit and contact failure due to scattered solder are less likely to occur, and it is possible to manufacture a semiconductor device whose reliability is less likely to be lowered.

根据实施方式一涉及的半导体装置的制造方法，由于在组装体形成工序中，第三焊锡材料层43的组成与除去助焊剂成分的第一焊锡材料层41的组成及除去助焊剂成分的第二焊锡材料层42的组成相同，因此，各焊锡材料层就会变得易于接合，并且在接合工序后的第一焊锡材料层、第三焊锡材料层以及第二焊锡材料层的接合强度会变得更高。According to the semiconductor device manufacturing method according to Embodiment 1, in the assembly forming process, the composition of the third solder material layer 43 is different from the composition of the first solder material layer 41 except the flux component and the second solder material layer 41 except the flux component. The composition of the solder material layer 42 is the same, therefore, each solder material layer will become easy to join, and the joint strength of the first solder material layer, the third solder material layer and the second solder material layer after the joining process will become higher.

此外，根据实施方式一涉及的半导体装置的制造方法，由于在组装体形成工序中，是在半导体芯片20上配置第一焊锡材料层41及第三焊锡材料层43、并在引线30上配置第二焊锡材料层42之后，将第三焊锡材料层43与第二焊锡材料层42重叠来形成组装体50，因此就可以易于形成第一焊锡材料层41及第二焊锡材料层42，并且处理也会变得容易。In addition, according to the semiconductor device manufacturing method according to Embodiment 1, since the first solder material layer 41 and the third solder material layer 43 are arranged on the semiconductor chip 20 and the third solder material layer is arranged on the lead 30 in the assembly forming process, After the second solder material layer 42, the third solder material layer 43 is overlapped with the second solder material layer 42 to form the assembly 50, so the first solder material layer 41 and the second solder material layer 42 can be easily formed, and the processing is also easy. will get easier.

根据实施方式一涉及的半导体装置的制造方法，由于焊锡40的厚度大于等于300μm，因此就能够缓和作用于半导体芯片20与引线30之间的焊锡40的应力(例如热应力)，从而在焊锡40中就不易产生裂纹等不良情况。这样一来，就能够制造可靠性不易下降的半导体装置。从该观点来说，为了更不易产生上述的不良情况，焊锡40的厚度最好是大于等于400μm，而焊锡40更为理想的厚度是大于等于500μm。According to the method of manufacturing a semiconductor device according to Embodiment 1, since the thickness of the solder 40 is equal to or greater than 300 μm, the stress (for example, thermal stress) acting on the solder 40 between the semiconductor chip 20 and the lead 30 can be relaxed, and the solder 40 It is not easy to produce cracks and other adverse conditions. In this way, it is possible to manufacture a semiconductor device whose reliability is less likely to be lowered. From this point of view, the thickness of the solder 40 is preferably equal to or greater than 400 μm, and more preferably, the thickness of the solder 40 is equal to or greater than 500 μm in order to make the above-mentioned disadvantages less likely to occur.

其次，根据实施方式一涉及的半导体装置的制造方法，由于在组装体形成工序S200中，是使用分配器来配置第一焊锡材料层41及第二焊锡材料层42，因此就能够准确且稳定地提供糊状的焊锡，从而就能够形成不易溢出焊锡且厚度偏差较少的第一焊锡材料层41及第二焊锡材料层42。Next, according to the semiconductor device manufacturing method according to Embodiment 1, since the first solder material layer 41 and the second solder material layer 42 are placed using the dispenser in the assembly forming step S200, it is possible to accurately and stably By providing paste solder, it is possible to form the first solder material layer 41 and the second solder material layer 42 which are less prone to solder overflow and have less variation in thickness.

【实施方式二】【Implementation Mode 2】

虽然实施方式二涉及的半导体装置的制造方法基本上具有与实施方式一涉及的半导体装置的制造方法相同的工序，但是其在配置第二焊锡材料层的位置上却与实施方式一涉及的半导体装置的制造方法的情况有所不同。即，在实施方式二涉及的半导体装置的制造方法的组装体形成工序中，在第一焊锡材料层配置工序后(参照图6(a))，在将第一焊锡材料层41、第三焊锡材料层43及第二焊锡材料层42配置于半导体芯片20上之后(参照图6(b))，将第二焊锡材料层42与引线30(形成有引线30、62、64的引线框)重叠来形成组装体50(参照图6(c))。Although the manufacturing method of the semiconductor device according to the second embodiment basically has the same steps as the manufacturing method of the semiconductor device according to the first embodiment, it differs from the semiconductor device according to the first embodiment in the position where the second solder material layer is disposed. The case of the manufacturing method is different. That is, in the assembly forming step of the semiconductor device manufacturing method according to Embodiment 2, after the first solder material layer arrangement step (see FIG. 6(a)), the first solder material layer 41, the third solder After the material layer 43 and the second solder material layer 42 are placed on the semiconductor chip 20 (refer to FIG. An assembly 50 is formed (see FIG. 6( c )).

虽然实施方式二涉及的半导体装置的制造方法在配置第二焊锡材料层的位置上与实施方式一涉及的半导体装置的制造方法的情况有所不同，但是其与实施方式一涉及的半导体装置的制造方法的情况同样是在组装体形成工序中，将焊锡材料44配置在发射极24与电极连接片32之间，所述焊锡材料44具有被配置于第一焊锡材料层41与第二焊锡材料层42之间的且不含有助焊剂的第三焊锡材料层43。通过使用这种方法，在不含有助焊剂的第三焊锡材料层43中，由于助焊剂不会在接合工序时(回流时)蒸发，并且第三焊锡材料层43部分的厚度也不会因助焊剂的蒸发而导致在接合工序后变薄，因此，就可以无需使接合工序前的(第一～第三焊锡材料层整体的)焊锡材料44的厚度变得过厚(比接合工序后的焊锡的厚度稍厚即可)。所以，即使是将引线30配置在焊锡材料44上也不易压坏焊锡材料44，从而就能够防止焊锡材料溢出到不希望的位置上。这样一来，就能够制造可靠性不易下降的半导体装置。Although the manufacturing method of the semiconductor device according to the second embodiment differs from the method of manufacturing the semiconductor device according to the first embodiment in the position where the second solder material layer is arranged, it is similar to the method of manufacturing the semiconductor device according to the first embodiment. The case of the method is also that in the assembly forming process, the solder material 44 is arranged between the emitter electrode 24 and the electrode connection piece 32, and the solder material 44 has a function of being arranged between the first solder material layer 41 and the second solder material layer. 42 and the third solder material layer 43 that does not contain flux. By using this method, in the third solder material layer 43 that does not contain flux, since the flux will not evaporate during the bonding process (during reflow), and the thickness of the third solder material layer 43 will not be affected by the flux. The evaporation of the flux leads to thinning after the bonding process, so it is not necessary to make the thickness of the solder material 44 (overall the first to third solder material layers) before the bonding process to become too thick (compared to the solder material layer after the bonding process). The thickness is slightly thicker). Therefore, even if the lead wire 30 is arranged on the solder material 44, the solder material 44 is less likely to be crushed, and the solder material can be prevented from overflowing to an undesired position. In this way, it is possible to manufacture a semiconductor device whose reliability is less likely to be lowered.

此外，根据实施方式二涉及的半导体装置的制造方法，由于组装体形成工序在发射极24与电极连接片32之间配置焊锡材料44，所述焊锡材料44具有被配置于第一焊锡材料层41与第二焊锡材料层42之间的且不含有助焊剂的第三焊锡材料层43，因此就能够制造将焊锡40的厚度保持在一定厚度以上的半导体装置。所以就能够缓和作用于半导体芯片20与引线30之间的焊锡40的应力(例如热应力)，从该观点来看也能够制造可靠性不易下降的半导体装置。In addition, according to the method of manufacturing a semiconductor device according to the second embodiment, the solder material 44 is disposed between the emitter electrode 24 and the electrode connection pad 32 due to the assembly forming process. Since the third solder material layer 43 between the second solder material layer 42 and does not contain flux, it is possible to manufacture a semiconductor device in which the thickness of the solder 40 is maintained at a certain thickness or more. Therefore, the stress (for example, thermal stress) acting on the solder 40 between the semiconductor chip 20 and the lead 30 can be alleviated, and from this point of view, it is also possible to manufacture a semiconductor device whose reliability is less likely to be lowered.

根据实施方式一涉及的半导体装置的制造方法，由于组装体形成工序在发射极24与电极连接片32之间配置焊锡材料44，所述焊锡材料44具有被配置于发射极24的表面且含有助焊剂的第一焊锡材料层41、以及被配置于引线30的电极连接片32的表面且含有助焊剂的第二焊锡材料层42，因此，就能够通过助焊剂在去除发射极24、电极连接片32以及第三焊锡材料层43的表面的掺杂物后的状态下进行接合，从而就能够制造焊锡40与半导体芯片20或引线30之间的密合强度较高的半导体装置。所以，就无需为了防止焊锡40与半导体芯片20之间的接合强度或焊锡40与引线30之间的接合强度变得低下而要在特殊的条件(在氢气氛下等)下实施接合工序，从而就能够防止接合工序变得繁杂。According to the semiconductor device manufacturing method according to Embodiment 1, the solder material 44 having a surface arranged on the emitter electrode 24 and containing auxiliary The first solder material layer 41 of the flux, and the second solder material layer 42 that is arranged on the surface of the electrode connection piece 32 of the lead 30 and contains flux, therefore, the emitter 24 and the electrode connection piece can be removed by the flux. 32 and the dopant on the surface of the third solder material layer 43 are bonded, so that a semiconductor device with high adhesion strength between the solder 40 and the semiconductor chip 20 or the lead 30 can be manufactured. Therefore, it is not necessary to carry out the bonding process under special conditions (under a hydrogen atmosphere, etc.) in order to prevent the bonding strength between the solder 40 and the semiconductor chip 20 or the bonding strength between the solder 40 and the lead 30 from becoming low. It is possible to prevent the bonding process from becoming complicated.

此外，根据实施方式二涉及的半导体装置的制造方法，由于是在半导体芯片20上配置第一焊锡材料层41、第三焊锡材料层43及第二焊锡材料层42之后，将第二焊锡材料层42与引线30重叠来形成组装体50，因此，第二焊锡材料层42与第三焊锡材料层43之间的对位就会变得容易，从而就能够简便地制造半导体装置。此外，由于第三焊锡材料层43是固体状的焊锡材料，因此就能够稳定地在表面上形成第二焊锡材料层42。In addition, according to the manufacturing method of the semiconductor device according to the second embodiment, after disposing the first solder material layer 41 , the third solder material layer 43 and the second solder material layer 42 on the semiconductor chip 20 , the second solder material layer 42 is overlapped with the lead 30 to form the assembly 50, the alignment between the second solder material layer 42 and the third solder material layer 43 becomes easy, and the semiconductor device can be manufactured simply. In addition, since the third solder material layer 43 is a solid solder material, the second solder material layer 42 can be stably formed on the surface.

由于实施方式二涉及的半导体装置的制造方法在除了配置第二焊锡材料层的位置以外的点上，具有与实施方式一涉及的半导体装置的制造方法相同的方法，因此其也具有实施方式一涉及的半导体装置的制造方法所具有的效果。Since the method of manufacturing a semiconductor device according to Embodiment 2 has the same method as the method of manufacturing a semiconductor device according to Embodiment 1 except for the position where the second solder material layer is disposed, it also has the same characteristics as those related to Embodiment 1. The effect of the manufacturing method of the semiconductor device.

以上虽然是根据上述的实施方式来说明本发明，但是本发明不受上述的实施方式所限定。在不脱离其主旨的范围内能够以各种方式来实施，例如也能够进行如下变形。As mentioned above, although this invention was demonstrated based on the said embodiment, this invention is not limited to the said embodiment. It can be implemented in various forms in the range which does not deviate from the meaning, for example, the following deformation|transformation is also possible.

(1)在上述实施方式中记载的材质、形状、位置、大小等只是示例，在不损坏本发明的效果的范围内能够进行变更。(1) The materials, shapes, positions, sizes, and the like described in the above-mentioned embodiments are merely examples, and changes can be made within the range that does not impair the effects of the present invention.

(2)虽然在上述实施方式一中，是在半导体芯片20上配置第一焊锡材料层41及第三焊锡材料层43之后，使配置于引线30表面的第二焊锡材料层42重叠来形成组装体50，并且在实施方式二中，是在半导体芯片20上配置第一焊锡材料层41、第三焊锡材料层43及第二焊锡材料层42之后，使引线30重叠来形成组装体50，但是本发明不受此限定。也可以是例如在实施半导体芯片搭载工序(参照图7(a))之后，对第三焊锡材料层43的一个面提供糊状的焊锡材料并配置第一焊锡材料层41，对第三焊锡材料层43的另一个面提供糊状的焊锡材料并配置第二焊锡材料层42，且在形成焊锡材料44后(参照图7(b))配置在半导体芯片20的发射极24上，在这之后，在焊锡材料44上通过配置引线30(引线框)来形成组装体50(参照图7(c))。此外，也可以是在引线30的电极连接片32上叠层第二焊锡材料层42、第三焊锡材料层43及第一焊锡材料层41后(形成焊锡材料44后)，在半导体芯片20的发射极24上配置焊锡材料44及引线30(引线框)。(2) Although in the above-mentioned first embodiment, after the first solder material layer 41 and the third solder material layer 43 are arranged on the semiconductor chip 20, the second solder material layer 42 arranged on the surface of the lead 30 is overlapped to form an assembly. body 50, and in Embodiment 2, after disposing the first solder material layer 41, the third solder material layer 43, and the second solder material layer 42 on the semiconductor chip 20, the leads 30 are overlapped to form the assembly 50, but The present invention is not limited thereto. For example, after implementing the semiconductor chip mounting process (refer to FIG. 7(a)), a pasty solder material is provided to one surface of the third solder material layer 43 and the first solder material layer 41 is arranged, and the third solder material layer The other side of the layer 43 provides paste solder material and configures the second solder material layer 42, and after forming the solder material 44 (refer to FIG. , the assembly 50 is formed by disposing the lead 30 (lead frame) on the solder material 44 (see FIG. 7( c )). In addition, after the second solder material layer 42, the third solder material layer 43, and the first solder material layer 41 are laminated on the electrode connection piece 32 of the lead 30 (after the solder material 44 is formed), the solder material layer 44 may be formed on the semiconductor chip 20. A solder material 44 and a lead 30 (lead frame) are arranged on the emitter 24 .

(3)在上述各实施方式中，虽然是将半导体芯片20来作为IGBT，但是本发明不受此限定。也可以是将半导体芯片20来作为其他三个端子的半导体元件(例如MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor))，还可以将半导体芯片20来作为两个端子的半导体元件(例如二极管)，更可以将半导体芯片20来作为大于等于四个端子的半导体元件(作为四个端子的半导体元件可以是例如晶闸管)。(3) In each of the above-mentioned embodiments, although the semiconductor chip 20 is used as an IGBT, the present invention is not limited thereto. It is also possible to use the semiconductor chip 20 as another three-terminal semiconductor element (such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)), or to use the semiconductor chip 20 as a two-terminal semiconductor element (such as a diode) Furthermore, the semiconductor chip 20 may be used as a semiconductor element with four terminals or more (the semiconductor element with four terminals may be, for example, a thyristor).

(4)在上述各实施方式中，虽然是将半导体装置设为具备一个半导体芯片，但是本发明不受此限定。例如，也可以是将半导体装置设为具备两个半导体芯片(参照图8)，还可以将其设为具备大于等于三个半导体芯片。(4) In each of the above-mentioned embodiments, although the semiconductor device is provided with one semiconductor chip, the present invention is not limited thereto. For example, the semiconductor device may be provided with two semiconductor chips (see FIG. 8 ), or may be provided with three or more semiconductor chips.

作为具备两个半导体芯片的半导体装置，例如可以想到以下这种将两个半导体芯片进行级联后的半导体装置(参照图8，变形例二涉及的半导体装置2)。在变形例二涉及的半导体装置2中，第一半导体芯片20a的发射极24a与第一引线30a电连接，并且第一半导体芯片20a的集电极22a经由第一基板10a的电路16a与第二引线30b连接的同时，经由第二引线30b与第二半导体芯片20b的发射极24b电连接，虽然未图示，但是第二半导体芯片20b的集电极22b经由电路16b与引线66连接。即使是在这种结构的半导体装置中，也能够由叠层了第一焊锡材料层、第三焊锡材料层及第二焊锡材料层的焊锡材料来形成第一半导体芯片20a的发射极24a与第一引线30a之间的焊锡、以及第二半导体芯片20b的发射极24b与第二引线30b之间的焊锡。As a semiconductor device including two semiconductor chips, for example, the following semiconductor device in which two semiconductor chips are cascaded is conceivable (see FIG. 8 , semiconductor device 2 according to Modification 2). In the semiconductor device 2 according to Modification 2, the emitter 24a of the first semiconductor chip 20a is electrically connected to the first lead 30a, and the collector 22a of the first semiconductor chip 20a is connected to the second lead via the circuit 16a of the first substrate 10a. 30b, is electrically connected to the emitter 24b of the second semiconductor chip 20b via the second lead 30b, and although not shown, the collector 22b of the second semiconductor chip 20b is connected to the lead 66 via the circuit 16b. Even in a semiconductor device having such a structure, the emitter 24a and the first semiconductor chip 20a of the first semiconductor chip 20a can be formed of a solder material layered with a first solder material layer, a third solder material layer, and a second solder material layer. The solder between the first lead 30a, and the solder between the emitter 24b of the second semiconductor chip 20b and the second lead 30b.

(5)在上述各实施方式中，虽然是将半导体装置设为：在半导体芯片的一个面上具有集电极，且在另一个面上具有发射极及栅电极的所说的纵向半导体装置，但是本发明不受此限定。例如，也可以是将半导体装置设为：在与基板侧是相反侧的面上具有全部电极的所说的横向半导体装置。(5) In each of the above-mentioned embodiments, the semiconductor device is a so-called vertical semiconductor device having a collector electrode on one surface of the semiconductor chip and an emitter electrode and a gate electrode on the other surface. The present invention is not limited thereto. For example, the semiconductor device may be a so-called lateral semiconductor device having all electrodes on the surface opposite to the substrate side.

(6)在上述各实施方式中，虽然在配置第一焊锡材料层及第二焊锡材料层时是使用分配器来提供焊锡材料，但是本发明不受此限定。例如，如有可能，也可以是通过印刷来提供焊锡材料(例如在实施方式一中，当在引线30上配置第二焊锡材料层42等时有效)，也可以是通过由焊锡供给器等送出的焊锡丝来提供焊锡材料，还可以是通过其他适当的方法来提供焊锡材料。(6) In each of the above-mentioned embodiments, the dispenser was used to supply the solder material when arranging the first solder material layer and the second solder material layer, but the present invention is not limited thereto. For example, if possible, the solder material may be provided by printing (for example, in the first embodiment, when the second solder material layer 42 is placed on the lead 30, etc., is effective), it may also be sent out by a solder supplier or the like. The solder wire can be used to provide the solder material, and other appropriate methods can also be used to provide the solder material.

符号说明Symbol Description

1…半导体装置；10、10a、10b…基板；12、12a、12b…芯片搭载面；14、14a、14b…绝缘性基板；16、16a、16b…电路；18、18a、18b…散热用金属板；20、20a、20b…芯片；22、22a、22b…集电极(第一电极)；24、24a、24b…发射极(第二电极)；26…栅电极；30、30a、30b、62、64、66…引线；32…电极连接片；34…外部连接端子；40、40a、40b、46…焊锡；41…第一焊锡材料层；42…第二焊锡材料层；43…第三焊锡材料层；44、45…焊锡材料；50…组装体；70…导线；80…树脂。1...semiconductor device; 10, 10a, 10b...substrate; 12, 12a, 12b...chip mounting surface; 14, 14a, 14b...insulating substrate; 16, 16a, 16b...circuit; 18, 18a, 18b...metal for heat dissipation plate; 20, 20a, 20b... chip; 22, 22a, 22b... collector (first electrode); 24, 24a, 24b... emitter (second electrode); 26... gate electrode; 30, 30a, 30b, 62 , 64, 66...Lead wire; 32...Electrode connecting piece; 34...External connection terminal; 40, 40a, 40b, 46...Solder; 41...First solder material layer; 42...Second solder material layer; 43...Third solder Material layer; 44, 45...solder material; 50...assembly body; 70...wire; 80...resin.

Claims (5)

1.一种半导体装置的制造方法，其制造的半导体装置具备：基板，其具有半导体芯片搭载面；半导体芯片，其被搭载于所述半导体芯片搭载面上，且具有形成在所述半导体芯片搭载面相向的面的相反侧的面上的电极；以及引线，其具有电极连接片，并且所述电极连接片经由焊锡而与所述电极相接合，所述半导体装置的制造方法的特征在于，包括：1. A method of manufacturing a semiconductor device, wherein the semiconductor device manufactured comprises: a substrate having a semiconductor chip mounting surface; a semiconductor chip mounted on the semiconductor chip mounting surface, and having a substrate formed on the semiconductor chip mounting surface; An electrode on a surface opposite to the facing surface; and a lead having an electrode connection piece, and the electrode connection piece is bonded to the electrode via solder, and the manufacturing method of the semiconductor device is characterized in that it includes : 组装体形成工序，在所述电极与所述电极连接片之间配置焊锡材料，所述焊锡材料具有被配置于所述电极的表面且含有助焊剂的呈糊状的第一焊锡材料层、被配置于所述电极连接片的表面且含有助焊剂的呈糊状的第二焊锡材料层、以及被配置于所述第一焊锡材料层与所述第二焊锡材料层之间的且不含有助焊剂的呈固体状的第三焊锡材料层相叠层后的构造，并且，所述组装体形成工序形成配置有所述基板、所述半导体芯片以及所述引线的组装体，使得所述电极与所述电极连接片成为夹着所述焊锡材料的相向状态；以及An assembly forming step, disposing a solder material between the electrode and the electrode connection sheet, the solder material having a paste-like first solder material layer disposed on the surface of the electrode and containing flux, The paste-like second solder material layer that is arranged on the surface of the electrode connection sheet and contains flux, and the paste that is arranged between the first solder material layer and the second solder material layer and does not contain flux The solder has a structure in which solid third solder material layers are laminated, and the assembly forming step forms an assembly in which the substrate, the semiconductor chip, and the leads are arranged so that the electrodes and The electrode connection pieces are in a facing state sandwiching the solder material; and 接合工序，在将所述焊锡材料熔融后，通过将所述焊锡材料固化来将所述电极与所述电极连接片经由所述焊锡进行接合，a joining step of joining the electrode and the electrode connecting piece via the solder by solidifying the solder material after melting the solder material, 其中，在所述组装体形成工序中，所述第三焊锡材料层的厚度在所述焊锡材料厚度的60％～90％的范围内，Wherein, in the assembly forming step, the thickness of the third solder material layer is within the range of 60% to 90% of the thickness of the solder material, 所述焊锡的厚度大于等于300μm。The thickness of the solder is greater than or equal to 300 μm. 2.根据权利要求1所述的半导体装置的制造方法，其特征在于：2. The method of manufacturing a semiconductor device according to claim 1, wherein: 其中，在所述组装体形成工序中，所述第三焊锡材料层的组成与除去助焊剂成分的所述第一焊锡材料层的组成及除去助焊剂成分的所述第二焊锡材料层的组成中的至少任意一方相同。Wherein, in the assembly forming step, the composition of the third solder material layer is the same as the composition of the first solder material layer excluding flux components and the composition of the second solder material layer excluding flux components. At least one of them is the same. 3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：3. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that: 其中，在所述组装体形成工序中，将所述第一焊锡材料层及所述第三焊锡材料层配置在所述电极上，并且在将第二焊锡材料层配置在所述电极连接片上后，将所述第三焊锡材料层与所述第二焊锡材料层重叠来形成所述组装体。Wherein, in the assembly forming step, the first solder material layer and the third solder material layer are arranged on the electrodes, and after the second solder material layer is arranged on the electrode connecting sheet, , forming the assembly by overlapping the third solder material layer and the second solder material layer. 4.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：4. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that: 其中，在所述组装体形成工序中，在所述半导体芯片上配置所述第一焊锡材料层、所述第三焊锡材料层及所述第二焊锡材料层后，将所述第二焊锡材料层与所述引线的所述电极连接片重叠来形成所述组装体。Wherein, in the assembly forming step, after disposing the first solder material layer, the third solder material layer, and the second solder material layer on the semiconductor chip, the second solder material layer A layer is overlapped with the electrode connection sheet of the lead to form the assembly. 5.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：5. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein: 其中，在所述组装体形成工序中，使用分配器来配置所述第一焊锡材料层及所述第二焊锡材料层。However, in the assembly forming step, the first solder material layer and the second solder material layer are arranged using a dispenser.
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JP7428595B2 (en) * 2020-06-08 2024-02-06 日立Astemo株式会社 Semiconductor device and method for manufacturing semiconductor device
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH067990A (en) * 1992-05-26 1994-01-18 Mitsubishi Electric Corp Solder material and joining method
JP2012049182A (en) * 2010-08-24 2012-03-08 Fuji Electric Co Ltd Method of manufacturing semiconductor device
CN103441109A (en) * 2013-06-19 2013-12-11 日月光半导体制造股份有限公司 Semiconductor element, semiconductor packaging structure and manufacturing method thereof
CN103996631A (en) * 2013-02-14 2014-08-20 富士电机株式会社 Method of manufacturing a semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5881945A (en) * 1997-04-30 1999-03-16 International Business Machines Corporation Multi-layer solder seal band for semiconductor substrates and process
JP3347279B2 (en) * 1997-12-19 2002-11-20 三菱電機株式会社 Semiconductor device and method of manufacturing the same
JP2001332686A (en) * 2000-05-19 2001-11-30 Sansha Electric Mfg Co Ltd Semiconductor module
JP2002261435A (en) * 2001-03-02 2002-09-13 Cimeo Precision Co Ltd Structure for laser diode sub-mount and its manufacturing method
JP4985129B2 (en) * 2007-06-12 2012-07-25 三菱電機株式会社 Bonded body, electronic module, and bonding method
JP5384913B2 (en) 2008-11-18 2014-01-08 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP5565147B2 (en) * 2010-06-30 2014-08-06 株式会社デンソー Manufacturing method of semiconductor module
JP2013183038A (en) * 2012-03-02 2013-09-12 Mitsubishi Electric Corp Semiconductor device
JP6697944B2 (en) 2016-04-27 2020-05-27 三菱電機株式会社 Power semiconductor device
JP7033889B2 (en) * 2017-11-10 2022-03-11 三菱電機株式会社 Power semiconductor devices, manufacturing methods for power semiconductor devices, and power conversion devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH067990A (en) * 1992-05-26 1994-01-18 Mitsubishi Electric Corp Solder material and joining method
JP2012049182A (en) * 2010-08-24 2012-03-08 Fuji Electric Co Ltd Method of manufacturing semiconductor device
CN103996631A (en) * 2013-02-14 2014-08-20 富士电机株式会社 Method of manufacturing a semiconductor device
CN103441109A (en) * 2013-06-19 2013-12-11 日月光半导体制造股份有限公司 Semiconductor element, semiconductor packaging structure and manufacturing method thereof

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