JPH0750726B2 - Semiconductor chip mounting body - Google Patents
Semiconductor chip mounting bodyInfo
- Publication number
- JPH0750726B2 JPH0750726B2 JP62111022A JP11102287A JPH0750726B2 JP H0750726 B2 JPH0750726 B2 JP H0750726B2 JP 62111022 A JP62111022 A JP 62111022A JP 11102287 A JP11102287 A JP 11102287A JP H0750726 B2 JPH0750726 B2 JP H0750726B2
- Authority
- JP
- Japan
- Prior art keywords
- electrical connection
- contact
- semiconductor chip
- connection contact
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はICチップに代表される、電気マイクロ回路を基
板上の端子電極群と接続するために用いる電気的接続接
点に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical connection contact represented by an IC chip and used for connecting an electric microcircuit to a terminal electrode group on a substrate.
従来の技術 従来、電気マイクロ回路の接点領域と回路基板上の導体
端子部との接続には、半田付けがよく利用されていた。
近年、たとえばICフラットパッケージ等の小型化と、接
続端子の増加により、接続端子間、いわゆるピッチ間隔
が次第に狭くなり従来の半田付け技術で対処することが
困難になってきた。また、最近では電卓，電子時計ある
いは液晶ディスプレイ等にあっては、裸のICチップをガ
ラス基板上の電極に直付けして実装面積の効率的使用を
図ろうとする動きがある。裸の半導体チップを半田付け
に代わり有効かつ微細な電気的接続を得る手段として、
たとえば半導体チップの入出力電極パッド上に公知のメ
ッキ技術により電気的接続接点を構成したり、特願昭61
-128653号公報に示されているように、金属ワイヤを用
い前記の入出力電極上に平坦な電気的接続接点を構成し
電気的接続接点と回路基板上の導体端子部との間に導電
性接着剤を設けて、接合することにより電気的接続を得
ようとする方法が提案されている。2. Description of the Related Art Conventionally, soldering has often been used to connect a contact area of an electric microcircuit and a conductor terminal portion on a circuit board.
In recent years, for example, due to downsizing of IC flat packages and the increase of connecting terminals, the so-called pitch interval between the connecting terminals is gradually narrowed, and it has become difficult to cope with the problem by the conventional soldering technique. In addition, recently, in calculators, electronic watches, liquid crystal displays, and the like, there is a movement to directly attach a bare IC chip to an electrode on a glass substrate to efficiently use a mounting area. As a means to obtain effective and fine electrical connection instead of soldering a bare semiconductor chip,
For example, an electric connection contact may be formed on the input / output electrode pad of a semiconductor chip by a known plating technique, or Japanese Patent Application No.
As disclosed in Japanese Patent No. 128653, a metal wire is used to form a flat electrical connection contact on the input / output electrode, and a conductive material is provided between the electrical connection contact and a conductor terminal portion on a circuit board. A method has been proposed in which an adhesive is provided and an attempt is made to obtain an electrical connection by joining.
発明が解決しようとする問題点 しかしながら上記のような構成では半導体チップの入出
力電極パッド上に形成された電気的接続接点の上部が平
坦な台形上に構成されており電気的接続接点と回路基板
上の導体端子部との間に形成した導電性接着剤は、押圧
接着した時界面で支え押し広げられるので導電性接着剤
が前記導体端子部の外へにじみ出し、広がり易いという
問題を有していた。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-mentioned configuration, the upper portion of the electrical connection contact formed on the input / output electrode pad of the semiconductor chip is formed into a flat trapezoid, and the electrical connection contact and the circuit board are Since the conductive adhesive formed between the upper conductive terminal portion and the upper conductive terminal portion is supported and spread at the interface when pressed and bonded, there is a problem that the conductive adhesive exudes to the outside of the conductive terminal portion and easily spreads. Was there.
本発明は上記の問題点に鑑みてなされたものであり、そ
の目的とする所は、微細かつ密に形成されている電気マ
イクロ回路上の入出力電極パッドと回路基板上の導体端
子部を信頼性よく接続しようとするものである。The present invention has been made in view of the above problems, and an object of the present invention is to reliably provide input / output electrode pads on an electric microcircuit and a conductor terminal portion on a circuit board that are finely and densely formed. I try to connect with good sexuality.
問題点を解決するための手段 上記問題点を解決するために本発明の電気的接続接点
は、基板上に設けた電極パッドの上に形成する突起状接
点であって、電極パッドに接触している第１の突起部
と、第１の突起部の上に形成され、かつ第１の突起部の
電極パッドと平行な断面積より小さな前記電極パッドと
平行な断面積を有する第２の突起部とを備えていること
を特徴とするものである。Means for Solving the Problems In order to solve the above problems, the electrical connection contact of the present invention is a protruding contact formed on the electrode pad provided on the substrate, And a second protrusion formed on the first protrusion and having a cross-sectional area parallel to the electrode pad that is smaller than the cross-sectional area parallel to the electrode pad of the first protrusion. It is characterized by having and.
作用 しかして本発明の上記した接点構造によれば、先端部が
小径でかつ突出した段差構成の接点領域を備えているの
で接続接点に設けた接点頂部と導体端子部とが当接し接
点底部の段差によって導電性接着剤層の厚みが規制さ
れ、導電性接着剤のにじみ，広がりがなく微細かつ密に
形成された電極間の接続を信頼性良く形成することがで
きる。According to the above-described contact structure of the present invention, however, since the tip portion has the contact area having the small diameter and the projecting step structure, the contact top portion and the conductor terminal portion provided on the connection contact come into contact with each other, and The thickness of the conductive adhesive layer is regulated by the step, and the fine and dense connection between the electrodes can be reliably formed without bleeding or spreading of the conductive adhesive.
実施例 以下本発明の一実施例の電気的接続接点について図面を
参照しながら説明する。Embodiments An electrical connection contact according to an embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の第１の実施例における電気的接続接点
の構成を示す断面図、第２図は電気的接続接点を回路基
板上の導体端子部に接合した時の構成を示す断面図であ
る。FIG. 1 is a sectional view showing the structure of an electrical connection contact in the first embodiment of the present invention, and FIG. 2 is a sectional view showing the structure when the electrical connection contact is joined to a conductor terminal portion on a circuit board. Is.
第１図および第２図において、１は半導体チップ、２は
入出力端子パッド、３は電気的接続接点、3aは接点底
部、3bは接点頂部、４は導電性接着剤層、５は回路基
板、６は導体端子部である。In FIGS. 1 and 2, 1 is a semiconductor chip, 2 is an input / output terminal pad, 3 is an electrical connection contact, 3a is a contact bottom, 3b is a contact top, 4 is a conductive adhesive layer, and 5 is a circuit board. , 6 are conductor terminal portions.
以上のように構成された電気的接続接点について以下第
１図および第２図を用いて詳細に説明する。The electrical connection contact configured as described above will be described in detail below with reference to FIGS. 1 and 2.
本発明の実施例では半導体チップ１上の入出力端子パッ
ド２に公知のホトエッチング法やメッキ技術を用いて、
材質が金からなる電気的接続接点３を構成する。この電
気的接続接点３は入出力端子パッド２に相当する接点底
部3a,および接点頂部3bからなり、接点頂部3bは接点底
部3aの外径から見て小径でかつ接点底部3aから階段状に
突出しており、その接点底部3aと接点頂部3bの高さは、
数10ミクロンに構成してある。なお前記突出部の高さに
ついては、階段状の構造を有するものであれば、その高
さは特に制限を加えるものではなく、さらに前記電気的
接続接点３の外径形状としては、円，角状など任意の形
状による構成が可能である。In the embodiment of the present invention, the I / O terminal pad 2 on the semiconductor chip 1 is formed by using a known photo-etching method or plating technique.
The electrical connection contact 3 made of gold is formed. The electrical connection contact 3 is composed of a contact bottom 3a corresponding to the input / output terminal pad 2 and a contact top 3b. The contact top 3b has a small diameter when viewed from the outer diameter of the contact bottom 3a and projects in a stepwise manner from the contact bottom 3a. The height of the contact bottom 3a and the contact top 3b is
It is composed of several tens of microns. The height of the protruding portion is not particularly limited as long as it has a stepwise structure, and the outer diameter shape of the electrical connection contact 3 is circular or square. It can be configured by any shape such as a shape.
上記のように構成された電気的接続接点３は第２図に示
すように導電性接着剤層４を介して回路基板５上の導体
端子部６と接着し電気的接続をする。接続方法として
は、まず導電性接着剤層４を電気的接続接点３上にスタ
ンピング法などにより転写して構成する。次いで電気的
接続接点３に導電性接着剤層４を構成した半導体チップ
１と回路基板５とを第２図に示すように導電性接着剤層
４を回路基板５の導体端子部６と対向させ位置合せした
後フリップチップボンタニ等を用いて押圧接着する。こ
の時前記導電性接着剤の硬化はホットプレートやオーブ
ンにより加熱し実施する。As shown in FIG. 2, the electrical connection contact 3 configured as described above is bonded to the conductor terminal portion 6 on the circuit board 5 via the conductive adhesive layer 4 to make an electrical connection. As a connection method, first, the conductive adhesive layer 4 is transferred onto the electrical connection contact 3 by a stamping method or the like. Next, the semiconductor chip 1 having the conductive adhesive layer 4 formed on the electrical connection contact 3 and the circuit board 5 are made to face the conductive adhesive layer 4 to the conductor terminal portion 6 of the circuit board 5 as shown in FIG. After aligning, press-bonding is performed using a flip chip bond or the like. At this time, the conductive adhesive is cured by heating with a hot plate or an oven.
以上のようにして入出力端子パッド２に電気的接続接点
３を形成した半導体チップ１と回路基板５上の導体端子
部６とを電気的に接続できる。As described above, the semiconductor chip 1 having the electrical connection contact 3 formed on the input / output terminal pad 2 and the conductor terminal portion 6 on the circuit board 5 can be electrically connected.
なお、実施例では電気的接続接点３の材質を金とした
が、その材質は金に限定されるものでなくニッケル，銅
を使用しても差支えない。Although the material of the electrical connection contact 3 is gold in the embodiment, the material is not limited to gold, and nickel or copper may be used.
発明の効果 以上説明したように、本発明の電気的接続接点の構成に
よれば基板上に設けた電極パッドの上に第１の突起部
と、その第１の突起部の上に形成され、かつ第１の突起
部の電極パッドと平行な断面積より小さな断面積を有す
る第２の突起部とを備えた２段構造の接点領域からなる
ので回路基板との接続に際して接続接点の先端部に設け
た接点頂部と接点底部の段差によって導電性接着剤の厚
みが規制されるため導電性接着剤のにじみ，広がりがな
く微細接続が可能となり実用上極めて価値が高い。As described above, according to the structure of the electrical connection contact of the present invention, the first protrusion is formed on the electrode pad provided on the substrate, and the first protrusion is formed on the first protrusion. Also, since the contact region has a two-step structure including the electrode pad of the first protrusion and the second protrusion having a cross-sectional area smaller than the parallel cross-sectional area, the tip end of the connection contact at the time of connection with the circuit board is formed. Since the thickness of the conductive adhesive is regulated by the step difference between the contact top and the contact bottom provided, the conductive adhesive does not bleed or spread and fine connection is possible, which is extremely valuable in practical use.
第１図は本発明の一実施例における電気的接続接点の断
面図、第２図は第１図の電気的接続接点を構成した半導
体チップを回路基板上の導体端子部と接続した時の断面
図である。 １……半導体チップ、２……入出力端子部、３……電気
的接続接点、3a……接点頂部、3b……接点底部、４……
導電性接着剤、５……回路基板、６……導体端子電極。FIG. 1 is a cross-sectional view of an electrical connection contact in one embodiment of the present invention, and FIG. 2 is a cross-section when a semiconductor chip constituting the electrical connection contact of FIG. 1 is connected to a conductor terminal portion on a circuit board. It is a figure. 1 ... semiconductor chip, 2 ... input / output terminal, 3 ... electrical connection contact, 3a ... contact top, 3b ... contact bottom, 4 ...
Conductive adhesive, 5 ... Circuit board, 6 ... Conductor terminal electrode.
Claims (2)
した構成であって、前記半導体チップの入出力端子部上
に第１の突起部と、前記第１の突起部の上に形成されか
つ前記第１の突起部の前記入出力端子部と平行な断面積
より小さな前記入出力端子部と平行な断面積を有する第
２の突起部とを備えた電気的接続接点を形成し、前記電
気的接続接点と前記基板上の前記端子電極部とが導電性
接着剤を介して電気的に接続されていることを特徴とす
る半導体チップの実装体。1. A structure in which a semiconductor chip is mounted on a terminal electrode portion on a substrate, wherein a first protrusion portion is formed on an input / output terminal portion of the semiconductor chip, and is formed on the first protrusion portion. And an electrical connection contact having a second protrusion having a cross-sectional area parallel to the input / output terminal portion smaller than a cross-sectional area parallel to the input / output terminal portion of the first protrusion, A semiconductor chip mounting body, wherein an electrical connection contact and the terminal electrode portion on the substrate are electrically connected via a conductive adhesive.
銅で構成されていることを特徴とする特許請求の範囲第
１項記載の半導体チップの実装体。2. The semiconductor chip mounting body according to claim 1, wherein the electrical connection contact is made of gold, nickel or copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111022A JPH0750726B2 (en) | 1987-05-07 | 1987-05-07 | Semiconductor chip mounting body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111022A JPH0750726B2 (en) | 1987-05-07 | 1987-05-07 | Semiconductor chip mounting body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63275127A JPS63275127A (en) | 1988-11-11 |
| JPH0750726B2 true JPH0750726B2 (en) | 1995-05-31 |
Family
ID=14550407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111022A Expired - Lifetime JPH0750726B2 (en) | 1987-05-07 | 1987-05-07 | Semiconductor chip mounting body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750726B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666355B2 (en) * | 1988-12-16 | 1994-08-24 | 松下電器産業株式会社 | Semiconductor device mounting body and mounting method thereof |
| JPH0749794Y2 (en) * | 1989-03-15 | 1995-11-13 | 三菱マテリアル株式会社 | Gold bump for wireless bonding |
| US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
| JPH04155835A (en) * | 1990-10-18 | 1992-05-28 | Mitsubishi Electric Corp | Manufacture of integrated circuit device |
| WO1994024694A1 (en) * | 1993-04-14 | 1994-10-27 | Amkor Electronics, Inc. | Interconnection of integrated circuit chip and substrate |
| DE4334715B4 (en) * | 1993-10-12 | 2007-04-19 | Robert Bosch Gmbh | Method for assembling components provided with electrical connections |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| KR19980044255A (en) * | 1996-12-06 | 1998-09-05 | 황인길 | Lead Finger Structure of Flip Chip Substrate |
| JPH1145954A (en) * | 1997-07-28 | 1999-02-16 | Hitachi Ltd | Flip chip connection method, flip chip connection structure, and electronic device using the same |
| CN101385402B (en) | 2006-02-13 | 2012-03-21 | 松下电器产业株式会社 | Circuit board and process for producing the same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4952973A (en) * | 1972-09-22 | 1974-05-23 | ||
| JPS57106155A (en) * | 1980-12-24 | 1982-07-01 | Hitachi Ltd | Semiconductor device |
| JPS604230A (en) * | 1983-06-21 | 1985-01-10 | Sharp Corp | Bonding method of semiconductor chip |
| JPS60240181A (en) * | 1984-05-14 | 1985-11-29 | 松下電器産業株式会社 | Electronic part |
| JPS6171651A (en) * | 1984-09-17 | 1986-04-12 | Hitachi Ltd | Input/output terminals of complex electronic circuits |
| US4661192A (en) * | 1985-08-22 | 1987-04-28 | Motorola, Inc. | Low cost integrated circuit bonding process |
-
1987
- 1987-05-07 JP JP62111022A patent/JPH0750726B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63275127A (en) | 1988-11-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |