JPS63239697A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To change a microcode without complicating a system by arranging memories to be rewritten/erased in order to change a microcode in a mask ROM in the seam address space, and while considering the degree of integration and economical efficiency, integrating these memories so as to optimize respective factors. CONSTITUTION:In a system controlled by a microcode, the mask ROM storing the microcode and the rewritable/erasable memory for writing a corrected microcode when the change of the microcode in the ROM 3 is required are arranged on the same address space of the same chip, a RAM 2 is also mounted on the same chip, and the storage capacity values of respective memories are determined and integrated so that the degree of integration and the economical efficiency are considered and optimized. Consequently, the microcode stored in the mask ROM 3 can be changed by converting the memory into a non- volatile memory and then writing the microcode therein, so that it is unnecessary to write the microcode in the area of the RAM 2 every time a power source is turned on.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology that is particularly effective when applied to semiconductor integrated circuits and systems incorporating semiconductor storage devices. This invention relates to effective technology that can be used in systems that perform (retention/erase).

[Prior Art] As a method of controlling the operation of an electronic computer, there is a method using microcode. Conventionally, the microcode is masked R.
Although OM is used, if a problem occurs in the control method, it is necessary to change part of the microcode. As a quick way to make this change to your existing system,
There is a method in which a RAM area is placed in the same address area as the microcode area of the ROM, the defective ROM code area is masked, and the corrected code is written to the RAM area when the system is started to enable normal operation.

[Problems to be solved by the invention] However, in the above-mentioned prior art, when the power is cut off, R
Since the modified microcode written in the AM will be erased, the microcode will be transferred to the RAM every time the power is turned on.
had to write in. Furthermore, in the above-mentioned conventional technology, it was necessary to check whether the microcode was written normally every time the microcode was written. Therefore.

There was a problem that the system became complicated.

An object of the present invention is to enable a system controlled by one microcode to substantially change the microcode stored in a mask ROM without complicating the system.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in a system controlled by microcode stored in a mask ROM, on the same chip,
A mask ROM in which microcode is stored, and if it is necessary to change the microcode in the mask ROM, a rewritable and erasable memory into which the modified microcode is written is placed in the same address space and on the same chip. RAM is installed in the memory, and the storage capacity of each memory is determined and integrated to be optimal in consideration of the degree of integration and economic efficiency. [Operation] If the above method is selected, mask ROM Changes to the microcode stored in the memory can be made by writing the changed microcode to non-volatile memory, eliminating the need to write the microcode to the RAM area every time the power is turned on, and eliminating the need to check the microcode. It turned out to be a good thing.

The above objective of being able to change the microcode without complicating the system can be achieved.

[Example] An example of the present invention will be described below with reference to FIG. The semiconductor device ill includes RAM2, mask ROM3, and, for example, E
It has a rewritable ROM4 like FROM. Furthermore, in this embodiment, a decoder for selecting these storage devices and a mask ROM 3 that is found to be defective are provided.
An address switching control unit 5 including a patching circuit for masking a part of the storage area and switching the selected address to the EFROM 4 is integrated in the same chip.

Furthermore, within the semiconductor device ill is a write control circuit 6 for controlling write timing of the EPROM 4, etc.
An address buffer section 7 for transferring addresses of RAM2, ROM3, and EPROM4 is provided.

In this embodiment, the RAM 2, mask ROM 3,
The storage capacity of the EPROM 4 is determined based on a graph as shown in FIG. 2, in which the horizontal axis represents the degree of integration (bits/chip) and the vertical axis represents cost performance (cost per unit bit).

In general, the storage capacity required for a system is less ROM and larger RAM, whereas ROM has a higher integration density.
RAM is low in density. Therefore, considering the degree of integration of RAM and ROM integrated in a semiconductor memory device, 1For example, in FIG. 2, if point A (integration degree A) is ROM, RAM is at point B (
In this graph, the curve Y shows the yield factor for cost performance, and the curve S shows the integration factor for cost performance. As the curve rises, the cost performance deteriorates, and the curve increases. As the price declines, cost performance improves.

As the graph shows, as the degree of integration increases, the cost performance deteriorates due to the yield factor, and the negative impact on cost performance due to the degree of integration factor decreases.

On the other hand, as the degree of integration decreases, the cost performance deteriorates due to the degree of integration factor, and the negative impact on cost performance due to the yield factor decreases. In other words, 1 point (
As shown by A+B), mask ROM3, RAM2 . EP
Optimal point when integrating ROM4 on the same chip (A+B)
exists.

In this case, A indicates the degree of integration of the ROM, and B indicates the degree of integration of the RAM. That is, in this embodiment, the ROM is integrated with the degree of integration A, and the RAM is integrated with the degree of integration B.

In this case, if the storage capacity necessary for the system cannot be secured due to consideration of cost performance, the insufficient storage capacity may be supplemented with a separate chip.

FIG. 3 shows a block diagram when the present invention is applied to a single-chip microcomputer.

In the figure, a CPU 29 having a data processing function, a semiconductor internal control unit 30 including input/output circuits, etc., and a RAM 2
, ROM 3 , and EPROM 4 are connected to each other by a bus 31 . The semiconductor internal storage device 28 stores the entire address space 17 as shown in FIG.
The basic storage area 12 requires a ROM as a fixed program area for hardware self-diagnosis at system start-up, system configuration check, etc. This ROM
As for the mask ROM area 14 and the rewritable EP
An external writing ROM area 15 using ROM is provided. The other areas are set as the RAM area 13.

The RAM 2, ROM 3, and EPROM 4 are integrated by determining the capacity of each memory in accordance with the graph shown in FIG. 2 so as to optimize cost performance. As a result, the RAM area 1 has insufficient capacity.
The deficit 13' of 3 is replenished by individual chips.

An embodiment of the address change method will be described using FIG. 5.

In the address changing method shown in the figure, ROM storage element matrix (hereinafter referred to as ROM address) 2
0 or data stored in the EPROM storage element matrix (hereinafter referred to as EPROM array) 21 is outputted via the gate group G1. That is, the output of ROM array 20 and the output of EPROM array 2
The output of 1 is input to the exclusive OR gate group G1, and when data is read out, a signal "0" is supplied from the EPROM array 21 to the other input terminal of each gate forming the gate group G1. It's like that.

Further, when data is read from the EPROM array 21, the signal #Olj is supplied from the ROM array 20 to the gate group G1.

If the data stored in the storage area Ai of the ROM array 2o is correct, the decoder 22 outputs a decode signal to the ROM array 20 to select the storage area Ai of the ROM array 20 by specifying the original address. by this.

Data stored in storage area Ai of ROM array 20 is output via gate group G1.

On the other hand, if a problem occurs in the microcode stored in the storage area of the ROM array 20, the EPROM array 2
A correct microcode is written in one predetermined storage area, for example, storage area A m + x, the address is changed, and the changed address is supplied to the decoder 23. Then, the decoder 22 supplies the EPROM array 21 with a decode signal for selecting the storage area Am+x, and the EPROM array 21 selects the gate group G.
Correct data is output via 1.

Next, a second embodiment of the address translation method will be described using FIG. 6.

In the figure, an address searchable rewritable ROM 2 in which data for selecting a word line of the ROM array 20 is written.
4. Address search rewritable ROM 2 into which data for selecting the word 5 line of the EPROM array 21 is written.
5 is provided.

If the data in the ROM array 20 is correct, the address search rewritable ROM 24 outputs a signal "1" to one input terminal of each AND gate making up the gate group G2, regardless of the decode signal supplied from the decoder 22. supply On the other hand, if a malfunction occurs in the microcode stored in a predetermined storage area of the ROM array 20, the data in the address searchable and rewritable ROM 24 is rewritten, the predetermined storage area is selected by the decoder 22, and the address The searchable and rewritable ROM 24 supplies a signal "O" to one input terminal of each AND gate constituting the gate group G2.

The address search rewritable ROM 25 is the ROM array 20
If the data is correct, the signal "O" is supplied to one input terminal of each AND gate constituting the gate G3, regardless of the decode signal supplied from the decoder 23. On the other hand, if a problem occurs with the data stored in a predetermined storage area of the ROM array 20, the data in the address search rewritable ROM 25 is rewritten, and when the predetermined storage area is selected by the decode signal, the address The searchable rewritable ROM 25 performs the AND operation of each gate group G3.
A signal "1" is supplied to one input terminal of the gate.

For example, if a problem occurs in the data stored in the storage area Ai of the ROM array 20, the data in the address searchable and rewritable ROM 24 is rewritten with data that masks the storage area Ai. Also, the address of the EPROM array 21, for example, A, corresponds to the reference address.
The correct data that should originally be stored in Ai in the storage area of the ROM array 20 is written to m + x, and the data in the address searchable and rewritable ROM 25 is
Change the microcode in +X so that it can be output from gate G4. As a result, correct data is output from the EPROM array 21 instead of the ROM 20 via the gate group G4 using the same reference address as before the change.

A block diagram of another address translation method is shown in FIG. In the same figure, address search rewritable CAM (co
tent addressable RAM) 40.4
1 are provided, and these CAMs 40 and 41 have the functions of the address retrieval and rewritable ROM and decoder shown in FIG. If a problem occurs in the data stored in a predetermined storage area of the ROM array 20, the address to be hit in the address retrieval/rewritable CAM 40 is masked. In addition, correct data is written to the EPROM array 21, and the address searchable and rewritable CAM 41
The necessary reference address is entered in the field. As a result, when an address is supplied, correct data is output from the EPROM array 21 via the gate group G4.

According to the above embodiment, when applied to a microprocessor using a microprogram control method, the microcode R
If there is an error in the microcode in OM or R
If a part of the microcode in the OM is changed, rewritable and erasable memory on the same chip is placed in the same address space, and the changed microcode is written to nonvolatile memory to be stored in the ROM. Since the stored microprogram can be modified and changed, there is no need to write the changed microcode to RAM etc. every time the power is turned on, and there is no need to check whether the microcode has been written correctly every time it is written. Due to the action of ``sumu''.

The effect is that microprograms can be modified and changed without complicating the system.

Furthermore, according to the embodiment described above, the mask ROM in which the microcode is stored is provided on the same chip.

If it is necessary to change the microcode in the mask ROM, a rewritable and erasable memory into which the modified microcode is written is placed in the same address space, and a RAM is mounted on the same chip to increase the integration density. By determining the storage capacity of each memory to optimize it in consideration of economic efficiency and integrating them, it is possible to configure a system that uses multiple types of memory, and to avoid storage with small memory capacity and poor cost performance. By eliminating the need to individually mount devices, the effect of optimizing cost performance can be achieved.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. In the explanation, the invention made by the sound of the present invention is mainly applied to a system for writing and reading control programs, etc., which is the background field of application, but the present invention is not limited to this. However, it can be applied to microprocessors in general where there is a possibility that a defect may occur in a part of the microcode.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, on the same chip, RAM, a mask ROM in which a microcode is stored, and a rewritable/erasable memory for changing the microcode in the mask ROM are arranged in the same address space, and the integration level and economy are improved. By considering these factors and integrating them in an optimal manner, the microcode can be changed without complicating the system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a graph showing the relationship between cost performance and degree of integration for each memory, and Fig. 3 is a block diagram showing a more specific embodiment of the invention. FIG. 4 is a memory map showing address allocation to each memory in the semiconductor storage device. FIGS. 5 to 7 are block diagrams each showing an embodiment of the address translation method. 1... Semiconductor storage device, 2... RAM, 3...
ROM, 4... EPROM, 5... Address switching control section, 6... Write control circuit, 7...
・Address buffer section, 20... ROM storage element matrix, 21... EPROM storage element matrix, 22° 23.
... Decoder, 24.25 ... Address search rewritable ROM, 29 ... CPU, 30 ... Semiconductor internal control unit, 40.41 ... Address detection 2nd
Figure collection $ (c-・nt/zorough・) Figure 3 Figure 4

Claims (1)

[Claims] 1. A nonvolatile memory in which a read-only memory, a rewritable nonvolatile memory, and a readable and writable volatile memory are mounted on the same chip, and a program is stored therein. A semiconductor integrated circuit characterized in that a correct bit pattern is written in the rewritable non-volatile memory when a problem occurs in the programming of the memory area, and a circuit system is provided to select this correct information. . 2. The semiconductor integrated circuit according to claim 1, wherein the nonvolatile memory and the rewritable nonvolatile memory are arranged in the same address space. 3. On the same chip mentioned above, there is a mask ROM in which the microcode is stored, and if it is necessary to change the microcode in the mask ROM, a rewritable/erasable memory in which the modified microcode is written is placed in the same address space. In addition, RAM is mounted on the same chip, and the storage capacity of each memory is determined and integrated in such a manner that they are optimized in consideration of the degree of integration and economic efficiency. The semiconductor integrated circuit as described in Items 1 and 2.