JP2001043685A - Microcomputer incorporating eeprom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the number of times of rewriting guarantee of EEPROM without special software processing by deciding a write-in region responding to a selection signal generated in accordance with the number of data written in the prescribed address of EEPROM, and performing write-in of data. SOLUTION: A EEPROM memory section 3 has memory regions corresponding to addresses of X pieces and provided with regions having the prescribed addresses, for example, memory regions corresponding to only and address 5 and regions having EEPROM cells being plural words and N pieces of words (N is a integer of >=2). Delivery and receipt of data in an internal bus of a microcomputer 1 and the EEPROM section 3 are performed by an EEPROM control section 4. Also, writing data in the EEPROM 2 is performed by executing an instruction of a ROM 7 incorporated in the microcomputer 1 through a CPU 8. Therefore, data are varied simply by +1 by an instruction of a ROM 7, and it is specified that data performing rewriting every variation is rewritten in an address 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer with built-in electrically erasable and erasable nonvolatile memory (hereinafter referred to as "EEPROM"). The present invention relates to a microcomputer with built-in EEPROM used for data processing that changes to +1 or the like.

[0002]

2. Description of the Related Art Conventionally, a microcomputer with built-in EEPROM mounted on a vehicle has been used for processing data such as ODO and TRIP for indicating a traveling distance. Of these, the ODO data representing the total mileage is
Since the traveling distance simply changes by +1 for each basic unit distance such as 1 km or 1 mile and is rewritten to the EEPROM at any time, the number of rewriting to the EEPROM becomes extremely large.

[0003] Also, an EEPROM with a built-in microcomputer
Writing data to the OM is executed by a command in the built-in ROM or an external command, but it is necessary for a programmer to specify which address of the EEPROM to write.

[0004] For this reason, EEPR data such as ODO data is used.
When handling data that is expected to be rewritten more than the guaranteed number of rewrites of the OM cell alone, it is necessary for the programmer to consciously manipulate the address to be written. Therefore, there is a demand for a microcomputer with built-in EEPROM that has a high guarantee of the number of times of rewriting of the EEPROM cell, that is, has excellent endurance characteristics.

As a prior art for the purpose of improving the endurance characteristic of a nonvolatile semiconductor memory device, for example, as disclosed in Japanese Patent Application Laid-Open No. 07-057489, there is no change in data before and after rewriting data in a flash EEPROM. It has been proposed to improve the endurance characteristics by using a control circuit that does not rewrite the memory cells.

The technique disclosed in this prior art document compares stored data of a memory cell with newly rewritten data, and performs rewriting only on a memory cell whose data has changed before and after data rewriting. is there. However, when data that simply increases and changes, such as travel distance data used in a car or the like, is rewritten at any time, at least the least significant bit is always rewritten.

[0007]

In the above-described conventional example, data that is constantly rewritten, such as mileage, is stored in the EEP.
Since the data is written to the ROM, the memory cell to which such data is written immediately reaches the guaranteed number of rewrites.
Therefore, there is a problem that the life of the device is extremely short.
In order to solve this problem, software processing for changing the memory cell in which the travel data is written is required.

An object of the present invention is to provide a microcomputer with built-in EEPROM, in which the number of times of rewriting of the built-in EEPROM is assured and special software processing is not required.

[0009]

According to the present invention, a microcomputer with built-in EEPROM is provided with an EEPROM through a CPU.
A microcomputer with built-in EEPROM for writing data to M, a selection control unit for monitoring data to be written to a predetermined address of the EEPROM, and generating a selection signal corresponding to the number of data; Writing means for writing the data by determining a writing area of the EEPROM corresponding to the predetermined address. The selection control unit generates a detection signal when the data is equal to or greater than the set value.
(N is an integer of 2 or more) comparators, and a word that detects which comparator among the N comparators is generating the detection signal and generates the selection signal according to the detection result And a decoder. The N comparators are set values in proportion to the guaranteed number of rewrites of the memory cells constituting the EEPROM, and different numbers are provided as the set values. Another address different from the predetermined address is further set, and in response to the selection signal, other data is written to a write area of the EEPROM corresponding to the other address. The present invention further provides a microcomputer with built-in EEPROM having a CPU, an internal bus connected to the CPU, and an EEPROM control unit connected to the internal bus and controlling writing of data to the EEPROM. ,
The memory device further comprises a selection control means for changing a writing area of the EEPROM in accordance with a change in the number of data to be written to a predetermined address of the EEPROM.
The selection control unit includes N (N is an integer of 2 or more) comparators that generate a detection signal when the data is equal to or greater than the set value, and which comparator among the N comparators detects the detection signal. A word decoder for detecting whether a signal is generated and determining a write area of the EEPROM according to the detection result. Further, the present invention provides a microcomputer with built-in EEPROM for writing data to an EEPROM via a CPU, wherein a physical write area for N (N is an integer of 2 or more) words is stored in the EEPROM for a predetermined address of the EEPROM. Means for setting and writing the data to a predetermined one-word area of the N-word area according to the number of data to be written to the predetermined address.

[0010]

Next, a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, an EEPROM 2 incorporated in a microcomputer 1 has an EEPROM R composed of a cell array in which the number of times of rewriting as a single cell is M times.
It comprises an OM memory unit 3 and an EEPROM control unit 4. The memory unit 3 has a memory area corresponding to X addresses. Normally, a memory area corresponding to one address is one word. One of the features of the present invention is that
A memory area corresponding to only a predetermined address, for example, address 5, of the memory unit is physically provided with an area having EEPROM cells of N words (N is an integer of 2 or more), which is a plurality of words.

Internal bus of microcomputer 1 and EE
Data exchange in the PROM memory unit 3 is EEPRO
M control unit 4, but the EEPROM control unit 4
It includes a word selection control unit 6 for selecting which word among N words corresponding to the address 5 of the PROM memory unit 3 to exchange data.

The writing of data to the EEPROM 2 is performed by executing a command from a ROM 7 built in the microcomputer 1 via the CPU 8. Therefore, the instruction of the ROM 7 simply designates that the data to be changed by +1 and the data to be rewritten each time the change is changed to the address 5. Next, the address 5 having the N-word EEPROM cell and the word selection control unit 6 will be described in detail. FIG. 2 is a block diagram showing a configuration example of the address 5 and the word selection control unit 6 in the embodiment of the present invention.

In FIG. 2, the word selection control section 6 has comparators 101,..., N comparators up to a comparator 100 + N and a word decoder 9. If each comparator is the comparator 101, an EEPROM is used as the set value 401.
The guaranteed number of rewrites M + 1 for a single cell is set, and if the comparator is 100 + K, the set value 400 + K is set to M × K + 1.

Each of the comparators generates a detection signal (501 to 500 + N) when the data to be rewritten to the address 5, that is, the number of times of rewriting of the data is equal to or more than a set value. The word decoder 9 detects which comparator among the comparators generates the detection signal, and determines which word of the word 201,..., Word 200 + N of the address 5 is to be written with data according to the detection result. A write word selection signal 10 to be selected is generated (selection control unit). In response to the word selection signal 10, the EEPROM control section 4 performs writing on the corresponding word (writing means).

.., Word 200+
.., Flag bit 300+
N is added, and 1 is written to the flag bit of the selected word at the same time as data writing. Therefore, when reading data at address 5, address 5
Read word select signal 1 for flag bits of each word
By detecting 1 in the word decoder 9, it is possible to determine from which word to read. Next, FIG.
3 will be described with reference to FIG. EEPROM2 whose cell is guaranteed to be rewritten 20,000 times
As an example, at address 5, ODO data, that is, data that simply changes +1 from 0,
The instruction in the ROM 7 is set so as to be rewritten and stored as needed. In this case, the word selection control unit 6 of the address 5 includes the comparators 101, 102,..., And the comparator 110, and the set values 401, 402,. , ..., 200001.

Address 5 is composed of words 201,.
Word 210 and flag bit 30 in each word
1,..., Flag bits 310.

It is assumed that the data already stored at address 5 is 60000, and 60001 of newly rewritten data is rewritten to address 5. At this time, 6
The data of 0000 is written in the word 203. Rewrite data 6000 to address 5
1 is a comparator 101,..., A comparator 110 is a set value 401,
.., Are compared with the set values 410, respectively.

The comparators 101,..., 103 have output signals 501,
.., The output signal 503 becomes a detection signal, and the comparator 104,
.., The output signal 504 of the comparator 110 does not generate any signal because the newly rewritten data is smaller than the set value.

The output signal 501,..., Output signal 510 is detected by the word decoder 9, and the write word selection signal 10
Is generated, data is written to the word 204 at the address 5, and at the same time, 1 is written to the flag bit 304 added to the word 204.

Therefore, address 5 is 20,000 *
The number of rewrites is guaranteed up to 10 = 200000 times.
This means that the EPROM 2 has improved endurance characteristics. When reading the data at the address 5, when the storage data is 60001, 1 is written in the flag bits 301,..., 304, and the flag bits 305,. Since 0 has been written, the read word selection signal 11 is detected by the word decoder 9, the word 204 is selected, and the data of 60001 is read.

In this state, even if the power supply to the microcomputer 1 is cut off, the data in the EEPROM 2 is retained, so that the power supply to the microcomputer 1 again to read out the data at the address 5 in the EEPROM 2 , Word 204 is selected and 60001 data is read. Therefore, when reading the data at address 5, the word decoder 9 detects the read word selection signal 11 so that the data can be read at any time. Next, another embodiment of the present invention will be described. EEPR of ODO data showing total mileage of car
In synchronization with rewriting to OM, TRIP data representing the section traveling distance is also rewritten to EEPROM,
As for the number of times of rewriting to the EEPROM, TRIP data is equal to ODO data, and there is a problem that it is extremely large. Also, this TRIP data may be reset to 0 in the middle to indicate the section mileage,
Simply does not change +1.

Therefore, in the present embodiment, as shown in FIG. 4, the EEPROM memory unit 3 of the EEPROM 2 shown in FIG.
To address 12 different from address 5 simply by +1 like TRIP data.
In order to store data to be rewritten in synchronization with data to be rewritten to
It has an EPROM cell. This address 1
In No. 2, like TRIP data, it is reset on the way and the data to be written does not simply increase. However, since the switching control of the words in the address 12 is all performed by the word selection control unit 6, the word switching timing is the same as that of the address 5.

That is, in this embodiment, only the address 12 is further provided, and all other control units are controlled by the control unit associated with the address 5.

At the address 12, the rewriting is performed in synchronization with the data at the address 5, so that the word selection at the time of rewriting may be the same as the word selection at the address 5, so that the write word selection signal 10 can be used as it is. . Also, for word selection at the time of reading,
Since it may be the same as the address 5, the read word selection signal 11 of the address 5 can be used as it is, and it is not necessary to add a flag bit to the address 12.

In the above-described embodiment, an example in which the traveling distance is changed by +1 has been described. However, the present invention is not limited to the +1 change, and any data that changes by the same number, such as +2 and +3, can be used. Applicable. At that time, if the set value of the comparator is multiplied by the numerical value, other configurations may be the same as those of the above-described embodiment.

[0027]

According to the present invention, the first effect is EEP.
This means that the number of guaranteed rewrites of the ROM, that is, the endurance characteristic is improved. The reason is EEP
This is because a plurality of words can be provided at an address at which data such as the ODO data which simply changes by +1 and is rewritten at any time can be provided even if the guaranteed number of rewrites for a single cell of the ROM is determined. The second effect is that the user can easily create a program for rewriting the EEPROM. The reason for this is that data that is rewritten more than the guaranteed number of times of rewriting of a single cell is usually
When storing the data in the OM, it is necessary to devise a program such as changing the address so that the same address is not rewritten more than the guaranteed number of times. Absent.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer incorporating an EEPROM according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a word selection control unit shown in FIG.

FIG. 3 is a diagram illustrating a configuration of a word selection control unit illustrated in FIG. 1;

FIG. 4 is a block diagram of a microcomputer with a built-in EEPROM according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microcomputer 2 EEPROM 3 EEPROM memory part 4 EEPROM control part 5 Address 6 Word selection control part 7 ROM 8 CPU

Claims (7)

[Claims] 1. A microcomputer with built-in EEPROM for writing data to an EEPROM via a CPU, wherein a selection control for monitoring data to be written to a predetermined address of the EEPROM and generating a selection signal corresponding to the number of the data. And a write unit for determining a write area of the EEPROM corresponding to the predetermined address in response to the selection signal and writing the data.
Microcomputer with built-in ROM. 2. The method according to claim 1, wherein the selection control unit is configured to generate N (N is an integer of 2 or more) comparators that generate a detection signal when the data is equal to or greater than the set value, and select one of the N comparators. 2. The EEPROM according to claim 1, further comprising a word decoder for detecting whether the comparator generates the detection signal and generating the selection signal according to the detection result.
Built-in microcomputer. 3. The EEPROM according to claim 2, wherein the N comparators include the EEPROM.
3. The EEPROM according to claim 2, wherein the set values are set in proportion to the guaranteed number of times of rewriting of the memory cells constituting the single memory cell, and different numbers are provided as the set values.
OM built-in microcomputer. 4. The method according to claim 1, wherein another address different from the predetermined address is further set, and another data is written in an EEPROM write area corresponding to the other address in response to the selection signal. E described in item 1
A microcomputer with built-in EPROM. 5. A microcomputer with built-in EEPROM, comprising: a CPU; an internal bus connected to the CPU; and an EEPROM control unit connected to the internal bus and controlling writing of data to the EEPROM. A selection control means for changing a writing area of the EEPROM in accordance with a change in the number of data to be written to a predetermined address of the EEPROM. 6. The selection control unit includes N (N is an integer of 2 or more) comparators that generate a detection signal when the data is equal to or greater than a set value, and any one of the N comparators. 6. The microcomputer with built-in EEPROM according to claim 5, further comprising: a word decoder for detecting whether the comparator generates the detection signal and determining a write area of the EEPROM according to the detection result. 7. A microcomputer with built-in EEPROM for writing data to an EEPROM via a CPU, wherein a physical write area for N (N is an integer of 2 or more) words for a predetermined address of the EEPROM is stored in the EEPROM.
ROM, and according to the number of data to be written to the predetermined address,
EEP, comprising means for writing the data in a predetermined one-word area of the word area.
Microcomputer with built-in ROM.