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JPS63198364A - Mold-type integrated circuit - Google Patents

Mold-type integrated circuit

Info

Publication number
JPS63198364A
JPS63198364A JP3100287A JP3100287A JPS63198364A JP S63198364 A JPS63198364 A JP S63198364A JP 3100287 A JP3100287 A JP 3100287A JP 3100287 A JP3100287 A JP 3100287A JP S63198364 A JPS63198364 A JP S63198364A
Authority
JP
Japan
Prior art keywords
lead frame
chip
chips
mold
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3100287A
Other languages
Japanese (ja)
Inventor
Katsuharu Kimura
克治 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3100287A priority Critical patent/JPS63198364A/en
Publication of JPS63198364A publication Critical patent/JPS63198364A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To realize the adaptation to the high integration by a method wherein individual chips are mounted face-to-face with each other on both faces of a lead frame. CONSTITUTION:A chip 10 is mounted on one face a of a lead frame; a pad on this chip 10 is connected to individual stiches 15 at the lead frame by using a bonding wire 11. In the same manner, the individual stiches 15 at the lead frame are connected by using bonding wires 11, 21. Accordingly, the pad on the chip 10 and the pad on a chip 20 are connected by using the bonding wires 11, 21 via the stiches 15 at the lead frame. If the chips 10, 20 are mounted on both faces of the lead frame, the area for mounting the chips is almost doubled even with the identical size of a mold by this setup; accordingly, the shape of a mold IC chip is miniaturized; the high integration is realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はモールド型集積回路（ＩＣ）に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to molded integrated circuits (ICs).

〔従来の技術〕[Conventional technology]

従来、この種のモールド型ＩＣは、リードフレーム上に
１チツプ搭載されるものが一般的であるが、リードフレ
ームの同一面に複数のチップを搭載する場合もある。Conventionally, in this type of molded IC, one chip is generally mounted on a lead frame, but a plurality of chips may be mounted on the same surface of the lead frame.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のモールドＩＣは、リードフレーム上に１
チツプ搭載する場合には、チップサイズの最大値がモー
ルドの大きさで制限されること。The conventional molded IC described above has one on the lead frame.
When mounting a chip, the maximum chip size must be limited by the size of the mold.

あるいはディジタル・アナログ混在のＩＣ等においては
、廻り込みによるＳ／Ｎの劣化、その防止のためにチッ
プのエリアが必要となるが一般的であり、リードフレー
ムの同一面に複数のチップを搭載する場合には複数のチ
ップ間の配線等も必要となり、モールドの形状が大きく
なるか、あるいはチップを小さくする必要があり、高集
積化に向かないという欠点がある。Alternatively, in ICs with a mixture of digital and analog, a chip area is required to prevent S/N degradation due to rotation, but it is common to mount multiple chips on the same side of a lead frame. In this case, wiring between a plurality of chips is also required, and the shape of the mold becomes large or the chips need to be made small, which has the disadvantage that it is not suitable for high integration.

本発明の目的は、このような欠点を除き、高集積化に適
したモールド型ＩＣを提供することにある。An object of the present invention is to eliminate such drawbacks and provide a molded IC suitable for high integration.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のモールド型ＩＣの構成は、リードフレームの両
面にそれぞれ対向して各チップを搭載したことを特徴と
する。The structure of the molded IC of the present invention is characterized in that each chip is mounted facing each other on both sides of a lead frame.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ＞、（ｂ）、（ｃ）は本発明の一実施例を示
す正面図、そのＡ−Ａ’縦断面図および裏面図である。FIGS. 1(a), (b), and (c) are a front view, an AA' vertical sectional view, and a back view of an embodiment of the present invention.

リードフレームの一方の面（ａ）にはチップ１０を搭載
、このチップ１０上のパッドとリードフレームの各ステ
ッチ１５との間をボンディングワイヤー１１で接続して
いる。同様に、リードフレームの各々ステッチ１５の間
をボンディングワイヤー１１．２１で接続している。A chip 10 is mounted on one surface (a) of the lead frame, and bonding wires 11 connect pads on the chip 10 to each stitch 15 of the lead frame. Similarly, bonding wires 11 and 21 connect each stitch 15 of the lead frame.

従って、チップ１０上のパッドとチップ２０上のパッド
とはボンディングワイヤー１１．２１により、リードフ
レームのステッチ１５を介して接続されている。Therefore, the pads on the chip 10 and the pads on the chip 20 are connected by bonding wires 11.21 via the stitches 15 of the lead frame.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、リードフレームの両面に
チップを搭載することにより、同一のモールドの大きさ
で約２倍のチップ面積分が搭載可能となるなめ、モール
ドＩＣの形状を小型化できる効果がある。また、２チッ
プ間のアイソレーションはリードフレームを間に介して
いるため、十分骨られる。従って、例えば、２つのチッ
プをアナログ回路とディジタル回路との回路に分割すれ
ば、ディジタル回路からのアナログ回路への廻り込み等
が十分低減出来る効果がある。As explained above, by mounting chips on both sides of a lead frame, the present invention allows approximately twice the chip area to be mounted with the same mold size, thereby making it possible to reduce the size of the molded IC. effective. Furthermore, the isolation between the two chips is sufficiently ensured because the lead frame is interposed between them. Therefore, for example, if two chips are divided into an analog circuit and a digital circuit, it is possible to sufficiently reduce the input from the digital circuit to the analog circuit.

さらに、チップ分割することにより各チップの歩留りの
向上も期待出来、コスト低減の効果がある。また、チッ
プの設計も分割することにより、並列して設計出来るの
で開発期間の短縮も可能となる効果がある。Furthermore, by dividing into chips, the yield of each chip can be expected to be improved, which has the effect of reducing costs. Furthermore, by dividing the chip design, it is possible to design the chips in parallel, which has the effect of shortening the development period.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）、（ｃ）は本発明の一実施例の正
面図、縦断面図および裏面図である。 １０．２０・・・チップ、１１．２１・・・ボンディン
グワイヤー、１５・・・ステッチ、１６・・・つりピン
。 第１図 （Ｃ）Ａ’FIGS. 1(a), (b), and (c) are a front view, a longitudinal sectional view, and a back view of an embodiment of the present invention. 10.20... Chip, 11.21... Bonding wire, 15... Stitch, 16... Hanging pin. Figure 1 (C) A'

Claims (1)

【特許請求の範囲】[Claims] リードフレームの両面にそれぞれ対向して各チップを搭
載したことを特徴とするモールド型集積回路。A molded integrated circuit characterized by mounting chips facing each other on both sides of a lead frame.
JP3100287A 1987-02-13 1987-02-13 Mold-type integrated circuit Pending JPS63198364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3100287A JPS63198364A (en) 1987-02-13 1987-02-13 Mold-type integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3100287A JPS63198364A (en) 1987-02-13 1987-02-13 Mold-type integrated circuit

Publications (1)

Publication Number Publication Date
JPS63198364A true JPS63198364A (en) 1988-08-17

Family

ID=12319365

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3100287A Pending JPS63198364A (en) 1987-02-13 1987-02-13 Mold-type integrated circuit

Country Status (1)

Country Link
JP (1) JPS63198364A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5334875A (en) * 1987-12-28 1994-08-02 Hitachi, Ltd. Stacked semiconductor memory device and semiconductor memory module containing the same

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