JPS63301552A - Wiring substrate - Google Patents
Wiring substrateInfo
- Publication number
- JPS63301552A JPS63301552A JP13494887A JP13494887A JPS63301552A JP S63301552 A JPS63301552 A JP S63301552A JP 13494887 A JP13494887 A JP 13494887A JP 13494887 A JP13494887 A JP 13494887A JP S63301552 A JPS63301552 A JP S63301552A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output bumps
- power supply
- wiring board
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子装置等に使用される半導体部品全実装す
る配線基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring board on which all semiconductor components used in electronic devices and the like are mounted.
第４図は従来の配線基板の表面からの斜視図。 FIG. 4 is a perspective view from the surface of a conventional wiring board.
第５図はその裏面から見友斜視図全それぞれ示し友もの
である。これらの図において、配線基板本体１，１の半
導体部品実装スペース１２のまわりには、リード用パッ
ド１３が形成されており、このリード用パッド１３は、
信号線１４あるいは電源。FIG. 5 shows the entire perspective view from the back side. In these figures, lead pads 13 are formed around the semiconductor component mounting spaces 12 of the wiring board bodies 1, 1.
Signal line 14 or power supply.
グランドパターン１５にエフ裏面全面に形成される入出
力用バンプ１６に接続されていｔ（例えば特開昭５７−
１５５７４９号公報、特願昭５６−４０６４１号公報、
特開昭５９−１８８９４４号公報、特願昭５８−６２２
０６号公報）。The ground pattern 15 is connected to an input/output bump 16 formed on the entire back surface of the F (for example, JP-A-57-
Publication No. 155749, Japanese Patent Application No. 56-40641,
Japanese Patent Application Laid-Open No. 59-188944, Japanese Patent Application No. 58-622
Publication No. 06).
上述し九従来の配線基板は、裏面全体に入出力用バンプ
１６が形成されているので、表面周辺部に形成されてい
るリード用パッド１３と入出力用バンプ１６と′ｆ！：
接続する信号線１４が長くなジ、まｔ１信号線１４の存
在にエク電ζ；ス、グランドパターン１５に切欠きが生
じてしまい、電気抵抗が高くなるという欠点があった。In the above-mentioned nine conventional wiring boards, the input/output bumps 16 are formed on the entire back surface, so the lead pads 13 and the input/output bumps 16 formed on the periphery of the front surface are connected to 'f! :
Since the connecting signal line 14 is long, the presence of the t1 signal line 14 causes an electric shock, and a notch is formed in the ground pattern 15, resulting in a high electrical resistance.
したがって本発明は、前述した従来の問題に鑑みてなさ
れ念ものであり、その目的は、リード用パッドと入出力
用バンプとの間の信号線および電源、グランドパターン
の電気抵抗全低減させｔ配線基板を提供することにある
。Therefore, the present invention was devised in view of the above-mentioned conventional problems, and its purpose is to reduce the total electrical resistance of the signal line, power supply, and ground pattern between the lead pad and the input/output bump. The purpose is to provide the substrate.
本発明の配線基板は、配線基板本体の表面に半導体部品
を実装する領域を有し、この領域の周辺部に半導体部品
のリードと接線されるリード用パッドが形成され、裏面
に入出力用バンプが形成され、さらに配線基板本体の内
部にリード用パッドと入出力用バンプとを接続する信号
線お工び′電源。The wiring board of the present invention has a region for mounting semiconductor components on the surface of the wiring board main body, lead pads that are tangential to the leads of the semiconductor components are formed around this region, and input/output bumps on the back surface. is formed, and then signal lines are fabricated to connect the lead pads and input/output bumps inside the wiring board body.
グランドパターンが形成されておジ、入出力用バンプは
裏面の周辺部のみに配置され、入出力用バンプのうち、
電源、グランドに使用される入出力用バンプを内側に集
めて構成されている。The ground pattern is formed, and the input/output bumps are placed only on the periphery of the back side.
It consists of input/output bumps used for power and ground gathered inside.
本発明においては、リード用パッドと入出力用バンプと
の間の信号線が短縮されるとともに電源。In the present invention, the signal line between the lead pad and the input/output bump is shortened, and the power supply line is shortened.
グランドパターンの切欠きが軽減される。Notches in the ground pattern are reduced.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
２１図は本発明の一実施例による配線基板の縦断面図、
第２図は表面から見た一部破断斜視図。FIG. 21 is a longitudinal sectional view of a wiring board according to an embodiment of the present invention;
FIG. 2 is a partially cutaway perspective view seen from the surface.
第３図は裏面から見友一部破断斜視図である。これらの
図において、半導体基板本体１の主要面には半導体部品
実装スペース１を有し、この半導体部品実装スペース２
の周辺部には図示しない半導体部品のリードと接続され
るリード用パッド３が形成されており、このリード用パ
ッド３は半導体基板本体１内に形成された信号線４ある
いは電源。FIG. 3 is a partially cut-away perspective view from the back side. In these figures, the main surface of the semiconductor substrate body 1 has a semiconductor component mounting space 1, and this semiconductor component mounting space 2
A lead pad 3 connected to a lead of a semiconductor component (not shown) is formed around the periphery of the semiconductor substrate 1, and this lead pad 3 is connected to a signal line 4 or a power supply formed in the semiconductor substrate body 1.
グランドパターン５ｔ−介して裏面側周辺部に形成配置
されている入出力用バンプ６に接続されている。さらに
リード用パッド３と電、源グランドパターン５とに１っ
て接続される１を源、グランドとして使用する入出力バ
ンプ７は、入出力用バンプ６のうちの内側に集められて
形成されている。It is connected to input/output bumps 6 formed and arranged on the periphery of the back side via the ground pattern 5t. Further, the input/output bumps 7 which are connected to the lead pad 3 and the power source/source ground pattern 5 and which use 1 as a source and ground are formed to be gathered inside the input/output bumps 6. There is.
以上説明し几工うに本発明は、入出力用バンプを裏面の
周辺部に集めることに工す、信号機を短かくすることが
でき、また、電源、グランドパターンの信号線による切
欠き２少なくでき、電気抵抗を小さくできるとともに’
！ｔ＃、グランドに使用する入出力バンブを内側に集め
ることにエリ、さらに一層信号線を短かくでき、電源、
グランドパターンの切欠きを少なくでき、電気抵抗を一
層小さくできるという極めて優れた効果が得られる。As explained above, the present invention concentrates the input/output bumps on the periphery of the rear surface, thereby making it possible to shorten the length of the traffic signal, and to reduce the number of cutouts caused by signal lines in the power supply and ground patterns. In addition to reducing electrical resistance,
! t#, it is advantageous to gather the input/output bumps used for grounding inside, and the signal line can be further shortened, and the power supply,
Extremely excellent effects can be obtained in that the number of notches in the ground pattern can be reduced and the electrical resistance can be further reduced.
第１図は本発明の一実施例にＬる配線基板の縦断面図、
第２図（は第１図の表面から見比一部破断斜視図、第３
図は第１図の表面から見た一部破断斜視図、第４図は従
来の配線基板の一例を示す表面から見た一部破断斜視図
、第５図は第４図に示す基板蓄氷の裏面から見比一部破
断斜視図である。
１・・・・配、ｖｉ！基板本体、２・・・・半導体部品
実装スペース、３・・・・リード用パッド、４・・・・
信号線、５・・・・電源、グランドパタ・−ン、６・・
・・入出力用パッド、６・・・・電源、グランドに使用
する入出力バンブ。
第４図
第５図FIG. 1 is a vertical cross-sectional view of a wiring board according to an embodiment of the present invention;
Figure 2 (is a partially cutaway perspective view compared to the surface of Figure 1, Figure 3)
The figure is a partially cutaway perspective view of the surface shown in Fig. 1, Fig. 4 is a partially cutaway perspective view of an example of a conventional wiring board seen from the front, and Fig. 5 is a board ice accumulation shown in Fig. 4. FIG. 2 is a partially cutaway perspective view seen from the back side. 1... hai, vi! Board body, 2... Semiconductor component mounting space, 3... Lead pad, 4...
Signal line, 5...Power supply, ground pattern, 6...
...Input/output pad, 6...Input/output bump used for power supply and ground. Figure 4 Figure 5
Claims (2)
を有し、該領域の周囲に半導体部品のリードと接続され
るリード用パッドが形成され、かつ裏面に入出力用バン
プが形成されており、内部に該リード用パッドと該入出
力用バンプを接続する信号線および電源、グランドパタ
ーンが形成された配線基板において、該入出力用バンプ
を配線基板本体の裏面周辺部に集めて配置したことを特
徴とする配線基板。(1) The wiring board has an area on the front surface for mounting the semiconductor component, a lead pad connected to the lead of the semiconductor component is formed around the area, and input/output bumps are formed on the back surface. In a wiring board in which signal lines, power supply, and ground patterns connecting the lead pads and the input/output bumps are formed inside, the input/output bumps are arranged around the back surface of the wiring board main body. A wiring board characterized by:
用される入出力用バンプを内側に集めたことを特徴とす
る特許請求の範囲第１項記載の配線基板。(2) The wiring board according to claim 1, wherein among the input/output bumps, input/output bumps used for power supply and grounding are gathered on the inside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13494887A JPS63301552A (en) | 1987-06-01 | 1987-06-01 | Wiring substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13494887A JPS63301552A (en) | 1987-06-01 | 1987-06-01 | Wiring substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63301552A true JPS63301552A (en) | 1988-12-08 |
Family
ID=15140305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13494887A Pending JPS63301552A (en) | 1987-06-01 | 1987-06-01 | Wiring substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63301552A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027191A (en) * | 1989-05-11 | 1991-06-25 | Westinghouse Electric Corp. | Cavity-down chip carrier with pad grid array |
| US5293067A (en) * | 1991-05-23 | 1994-03-08 | Motorola, Inc. | Integrated circuit chip carrier |
| US5726493A (en) * | 1994-06-13 | 1998-03-10 | Fujitsu Limited | Semiconductor device and semiconductor device unit having ball-grid-array type package structure |
| US7592692B2 (en) * | 2005-10-20 | 2009-09-22 | Nec Electronics Corporation | Semiconductor device with a dummy electrode |
-
1987
- 1987-06-01 JP JP13494887A patent/JPS63301552A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027191A (en) * | 1989-05-11 | 1991-06-25 | Westinghouse Electric Corp. | Cavity-down chip carrier with pad grid array |
| US5293067A (en) * | 1991-05-23 | 1994-03-08 | Motorola, Inc. | Integrated circuit chip carrier |
| US5726493A (en) * | 1994-06-13 | 1998-03-10 | Fujitsu Limited | Semiconductor device and semiconductor device unit having ball-grid-array type package structure |
| US7592692B2 (en) * | 2005-10-20 | 2009-09-22 | Nec Electronics Corporation | Semiconductor device with a dummy electrode |
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