JPS63184073A - Peak value detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a peak value detection circuit used in devices that measure the height of pulse signals, such as cell analyzers, cell sorters, and blood cell counters.

(b) Conventional technology In cell analyzers and the like, a circuit shown in FIG. 9 has been conventionally used to detect the peak value of a pulse signal as shown in FIG. 11. This peak value detection circuit has an input terminal 21
A peak hold circuit 22 holds the peak value of the signal under test that is input to the A/D converter 23 that converts the held peak value into a digital signal. It is composed of a pulse presence detection circuit 24 that outputs a signal and a timing controller 25. In addition, the peak hold circuit 22 used in this peak value detection circuit has an output terminal and an input terminal of amplifiers 26 and 27 with an amplification degree of 1, as shown in FIG.
A diode 28 is connected, and a hold capacitor 29 and a reset transistor 30 are connected between the output terminal of the diode 28 and ground.

In this peak value detection circuit, the 11th
When the pulse signal shown in the figure is input, the peak hold circuit 2
2 outputs a pulse presence signal while the pulse signal is above the threshold value, and this signal is applied to the timing controller 25, as shown in FIG. The timing controller 25 controls A/A when the pulse presence signal disappears.
An A/D conversion start signal is sent to the D converter 23, and the A/D converter 23 starts a conversion operation. When the conversion operation is completed, an A/D conversion end signal is sent to the timing controller 25, and the timing controller 25 receives this and
A reset signal is sent to the peak hold circuit 22, turning on the transistor 30, discharging the charge in the capacitor 29 through the transistor 30, and turning on the peak hold circuit 22.
to be reset.

(c) Problems to be Solved by the Invention The conventional peak value detection circuit described above performs A/D conversion in response to disappearance of the pulse presence signal, although the peak value of the peak-held pulse is A/D converted. Therefore, depending on the waveform of the signal under measurement, it may take a considerable amount of time from the peak hold point to the start point of A/D conversion. Therefore, as shown in FIG. 8, if the second pulse signal Ps2 is inputted after the peak hold of the first pulse signal Ps and before the reset, this second pulse signal Ps There was a problem in that the peak value of the pulse signal Psz could not be measured.

In view of the above, this invention provides an early A
The present invention aims to provide a peak value detection circuit capable of starting /D conversion.

(d) Means for Solving the Problems The peak value detection circuit of the present invention includes a peak hold circuit that receives a signal under measurement as an input and holds the peak value, and converts the output of this peak hold circuit into a digital signal. A/
a D converter, a peak presence detection circuit that receives the input signal under measurement and the output of the peak hold circuit to detect the presence of a peak, and converts the A/D converter in response to the output of the peak presence detection circuit. It consists of a timing controller that starts the operation.

(E) Function In this peak value detection circuit, when the pulse signal shown in FIG. 11 is inputted, the peak hold circuit holds the pulse signal at its peak as shown in FIG.
Further, when the pulse signal shifts to fall, the presence of a peak is detected by the peak presence detection circuit, and in response to this peak presence signal, the timing controller causes the A/D converter to start A/D conversion operation. A early after holding
/D conversion is performed.

(f) Examples The present invention will now be explained in more detail with reference to Examples.

FIG. 1 is a block diagram of a peak value detection circuit showing one embodiment of the present invention.

The peak value detection circuit of this embodiment is similar to the conventional circuit shown in FIG. The device includes an A/D converter 3 that converts the signal into a signal to be measured, a pulse presence detection circuit 4 that receives the signal to be measured, and outputs a pulse presence signal if the signal is equal to or higher than a threshold value, and a timing controller 25.

This embodiment circuit further includes a peak presence detection circuit 6 which compares the input signal (signal under test) and the output of the peak hold circuit 2, and outputs a peak presence signal when the input signal becomes smaller than the peak hold output. It is characteristically equipped with. This peak presence detection circuit 6 compares the input signal with the output of the peak hold circuit 2, and when the input signal becomes smaller, a peak hold detection circuit 7 outputs a high signal, that is, a peak presence signal. The peak hold detection circuit 7 includes a timer 8 which outputs a high signal when the peak hold detection circuit 7 outputs a high signal for a predetermined period or more, and the output of the timer 8 is output to the timing controller 5. The specific configuration of the peak hold circuit 2 is as follows.
Something similar to that shown in the figure is used. Further, as shown in FIG. 2(a), the pulse presence detection circuit 4 includes a terminal 43 to which an input signal is input, and a voltage comparator 41 to which a threshold voltage TH set by a setting device 42 is manually input. , a pulse presence signal is output from the output terminal 44 when the input signal - is greater than the threshold voltage TH. Figure 2 (bl shows the input signal and threshold voltage T
H, and its output is as shown in FIG. 2(C).

In addition, as shown in FIG. 3 (al), the peak hold detection circuit 7 inputs the input signal to one input terminal 72 and the output of the peak hold circuit 2 to the other input terminal 73, and compares the two. Then, a high level signal is output from the output terminal 74 when the human input signal becomes smaller than the peak hold signal, that is, when the input signal starts to fall. The waveform of the signal is shown in FIG. 3(C).
The output waveform of is shown.

In the peak value detection circuit of this embodiment, if a pulse signal as shown in FIG. The peak is held for a predetermined period from the time when the signal starts to fall.On the other hand, the pulse presence detection circuit 4 holds the pulse presence signal as shown in FIG. Output.

Furthermore, when the input pulse signal starts to fall below the output of the peak hold circuit 2, the peak hold detection circuit 7 detects
At this point, a high level signal is output [Figure 4 (C)],
Outputs a signal that is in peak hold. This signal indicating that the peak is being held is input to timer 8.
As shown in FIG. 4(d), a predetermined time t elapses after the peak hold detection circuit 7 rises, and outputs a high level signal, that is, a signal indicating that the peak hold is valid.

When the timing controller 5 receives the peak hold valid signal from the timer 8, it inputs an A/D conversion start signal to the A/D converter 3 [FIG. 4(e)]. This A
/D change A/D conversion start signal is received, the A/D converter 3 starts the A/D conversion operation, and when the A/D conversion operation is completed, as shown in FIG.
An A/D conversion end signal indicated by fl is returned to the timing controller 5. The timing controller 5 uses this A/D
When the conversion end signal is received, as shown in FIG. 4(g),
A reset signal is manually input to the peak hold circuit 2. When the peak hold circuit 2 receives this reset signal, it resets the peak value that has been held up to that point, thereby completing a series of peak value detection operations [FIG. 4(a)].

In this embodiment circuit, for example, two signals P shown in FIG.
To explain the case where relatively close pulse signals similar to sl and Psz are input, as shown in FIG.
First, when the first pulse signal Ps is input, the peak value is held in the peak hold circuit 2, and when the peak hold is detected, the A/D is immediately
When the conversion begins and the A/D conversion is completed, the peak value held until then is reset. This cycle of peak hold, A/D conversion, and reset is much shorter than the conventional case shown in FIG. 8, since the period for determining peak hold is not conditioned on the presence or absence of pulse value detection. When a second pulse signal Psz is subsequently input, it becomes possible to hold the peak value of this pulse signal Psz. Following the peak hold and peak presence detection of this second pulse signal PS2,
By repeating /D conversion and resetting, even if relatively close pulse signals Ps+ and Psz are input, it becomes possible to detect and measure the peak values of both signals.

In addition, in this embodiment circuit, the peak hold detection circuit 7
The output is sent to the timing controller 5 via the timer 8.
For example, as shown in FIG. 7, if the pulse signal P to be measured contains noise P8 with a relatively short pulse period that is not desired to be measured, first,
Assuming that the noise P is held at its peak,
As shown in Fig. 7 (bl), during the peak hold due to the noise P, the measurement signal shown in Fig. 7 (al) fell from its maximum value and recovered to the same level as the peak value of the noise PH. When the output of the pulse presence detection circuit falls low again, the period of existence of this noise P is determined by timer 8.
If the period t is shorter than the set period t, the timer 8 will not output any peak hold valid signal as shown in FIG. 7(C).

However, in the case of the pulse signal P shown in FIG. 7(a), the presence of a peak is detected and the signal rises to high, as shown in FIG. However, if the peak hold is still in the state, the peak hold valid signal rises to high as shown in FIG. Since the conversion start signal is input to the A/D converter 3, A
/D conversion is not performed and only the peak value of pulse Ps is A/D conversion.
It will be converted to D. In other words, P during the signal.

Even if such noise is mixed in, it can be removed.

(g) Effects of the Invention According to this invention, a peak presence detection circuit is provided, and the output of the peak hold circuit is compared with the input signal, and when the input signal is smaller than the peak hold value, the peak hold is enabled. In response to this signal, the timing controller issues a conversion start command to the A/D converter, so there is no need to wait a long time after starting peak hold. Since A/D conversion is started without any delay, there is no wasted hold period, and even if two relatively close pulse signals are input, they can be identified and each peak value can be detected. There is an advantage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a peak value detection circuit showing an embodiment of the present invention, and FIG. A waveform diagram for explaining the operation, FIG. 3 (al
(bl fc) is a diagram showing a specific circuit of the peak hold detection circuit used in the example circuit and a waveform diagram for explaining its operation, and Fig. 4 is a diagram explaining the overall operation of the example circuit. FIG. 5 is a waveform diagram for explaining the general operation of the present invention. FIG. 6 is a waveform diagram for explaining the identification of two input pulses closer to each other by the above embodiment circuit. The figure is a diagram explaining the operation of identifying noise when it is superimposed on the input pulse.
A waveform diagram for explaining the problems of the conventional circuit when relatively close pulse signals are input, FIG. 9 is a circuit block diagram of the conventional peak value detection circuit, and FIG.
A specific circuit diagram of the peak hold circuit, FIG. 11 is a diagram showing an example of an input pulse signal, and FIG. 12 is a waveform diagram for explaining a conventional peak hold operation. 2: Peak hold circuit, 3: A/D converter, 5: Timing controller, 6: Peak hold presence detection circuit, 7: Peak hold detection circuit, 8: Timer. Figure 4<g)-1111]--9-=■1f- ・T-''L Do, Go9to procedural amendment (release) 1. Indication of the case 1985 Patent Application No. 174158 2. Name of the invention Peak value detection circuit 3. Relationship with the person making the amendment Patent applicant address 1 Nishinokyo Kuwabara-cho, Nakagyo-ku, Kyoto City Name (1)
99) Kinsei Seisakusho Co., Ltd. Representative Director and President Minoru Nishihejo 4, Agent Ki 604 Address 1 Kyoto Naka Building 5F, 3-3 Mibu Kayo Gosho-cho, Nakagyo-ku, Kyoto City November 4, 1988 (Shipping date 62. 11.24)7,
Contents of the amendment (1)' In the 15th line of the 12th page of the specification, the statement ``Second
Figures (a), (b), and (c) J are corrected to "Figure 2." (2) From line 17 to line 18 on page 12 of the specification, ``Fig. 3 (a) However) (C) J''
Correct it to "Figure 3". that's all

Claims (2)

[Claims] (1) A peak hold circuit that receives the signal under test as an input and holds the peak value, an A/D converter that converts the output of the peak hold circuit into a digital signal, and the input signal under test and the peak hold circuit. The present invention is characterized by comprising: a peak presence detection circuit that receives an output and detects the presence of a peak; and a timing controller that starts a conversion operation of the A/D converter in response to the output of the peak presence detection circuit. Peak value detection circuit. (2) The peak presence detection circuit includes a peak hold detection circuit that compares the signal under test with the output of the peak hold circuit and detects the peak point, and a timer that delays the output of the peak hold detection circuit for a certain period of time and derives it. A peak value detection circuit according to claim 1, which comprises: