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JPS63150930A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS63150930A
JPS63150930A JP61299639A JP29963986A JPS63150930A JP S63150930 A JPS63150930 A JP S63150930A JP 61299639 A JP61299639 A JP 61299639A JP 29963986 A JP29963986 A JP 29963986A JP S63150930 A JPS63150930 A JP S63150930A
Authority
JP
Japan
Prior art keywords
chip
bonding
conductive
pads
rubber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61299639A
Other languages
English (en)
Inventor
Takumi Suda
工 須田
Katsuhisa Aizawa
相沢　勝久
Akio Nakamura
昭雄 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Polymer Co Ltd
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Polymer Co Ltd
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Polymer Co Ltd, Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Polymer Co Ltd
Priority to JP61299639A priority Critical patent/JPS63150930A/ja
Publication of JPS63150930A publication Critical patent/JPS63150930A/ja
Priority to US07/391,412 priority patent/US4970780A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、簡単な構造でありながら信頼性が高く、薄型
化が可能であり、しかも安価な半導体集積回路（以下Ｉ
Ｃという）チップと配線基板とを接続してなる半導体装
置に関するものである。
（従来の技術とその問題点） ＩＣチップと各種配線基板（銅張ガラス布基材エポキシ
樹脂積層板、銅張ガラス布基材ポリイミド樹脂積層板、
銅張ポリイミド樹脂フィルム等）との接続は、通常第２
図に示すような、ＩＣチップよのアクティブエリア２の
周囲に配置した入出力端子（以下ボンディング・パッド
という）３を。
第３図に示すように、配線基板４上の電極５と金。
アルミニウム等の導線６でボンディングするワイヤボン
ディング方式で行われている。しがしながらこの方式で
は、ＩＣチップの集積度が増加するとボンディング・パ
ッド数が増すため、ボンディング・パッド自体およびそ
の配列ピッチを小さくして、チップの利用率低下を防止
する必要がある。
しかしそうすると、ボンディングするワイヤの位置決定
に高度な精密性が要求され、またボンディング・パッド
を個別にボンディングするため、作業の長時間化を招き
、量産が妨げられることば必至である。
このような高集積度化に伴う問題点を解決するため、第
４図に示すように、ＩＣチップ上上のボンディング・パ
ッド３に突状半田電極７を設け、配線基板上の電極５と
一括接続するフリップチップ方式が行なわれている。こ
れによれば導線６を使用しないので、作業も簡略化され
るが、半田電極数が多くなるとその特性や形状にばらつ
きを生じ、また配線基板の平面度の良否によって接合強
度も不均一となる。さらに半田電極の間隔が狭くなった
ときには湿気によるリークを防止する対策が必要である
。そのうえ大型のＩＣチップを接続する場合には、それ
と配線基板との熱膨張率の差によって生ずるストレスが
、半田電極との接合を破壊してしまうことが予想され、
電気的に信頼性のある接続が得られないという欠点があ
る。
さらに第５図に示したように、長尺のポリイミドフィル
ム８に銅箔をはり付け、これをエツチングして配線基板
と接続するための導線９を形成したＴＡＢ方式も知られ
ている。これは導線９が工Ｃチップや配線基板と一括し
て位置合せされるために位置決め精度が高く、かつ、接
続のための作業時間が短いという利点があるほか、前記
の熱膨張率の差違によるストレスをこの導線９が吸収す
るという利便性があるが、その反面子めＩＣチップのボ
ンディング・パッドにめっき等によって突起状電極（バ
ンプ）を設けるか、もしくは導線９の、ＩＣチップと接
続する部分をエツチング等によって突状部を形成しなけ
ればならず、ＩＣチップの製品歩留りを低下させる等コ
ストアップはまぬがれない。
（問題点を解決するための手段） 本発明はこのような問題点を解決したもので、これは半
導体集積回路チップの入出力端子と配線基板の電極とが
弾性を有する導電性突状体を介して接続されてなること
を特徴とする半導体装置である。
すなわち、ＩＣチップのボンディング・パッドと配線基
板の電極との間を弾性を有する導電性突状体を介して接
続するという簡単な方法によって、安定な動作を行なう
半導体装置を提供することに成功したのである。
以下に、本発明の装置を、添付の図面にもとづいて説明
する。
第１図は本発明の半導体装置の縦断面図で、ＩＣチップ
上のボンディング・パッド３の下に弾性を有する導電性
突状体（ゴムバンプ）１０を形成し、配線基板上の電極
に圧着して電気的に接続し、ついで公知の方法で全体を
樹脂１１により封止する。
このようにして得られた半導体装置はパッケージレスで
あるために占有面積がＩＣチップのサイズと等しくなる
ので小型化される。また従来のチップ・オン・ボード方
式では、ボンディングする前にＩＣの検査、スクリーニ
ングをすることができなかったが、これは適切な圧力を
加えれば外部回路と容易に導通させることができるので
、検査、スクリーニングを簡便に行なうことができると
いう利便性が与えられる。また、ゴムバンプがゴム弾性
を有しているので、ＩＣチップと配線基板との熱膨張係
数が整合していなくても、バンプがそのストレスを吸収
し導電路が破壊されることがないので高い信頼性が得ら
れ、配線基板が平面性の劣るものであっても、ゴム弾性
によってこれに追従させることもできる。さらにこの装
置はきわめて簡単な構成であるので安価に製造すること
ができるという有利性が与えられる。
本発明の装置を構成する配線基板は、銅張エポキシ樹脂
積層板、銅張ポリイミド樹脂積層板、銅張ポリイミド樹
脂フィルム等のような配線基板に電子回路を埋設、印刷
した回路板（以下ＰＣＢと略記する）の他、フリップチ
ップ方式、ＴＡＢ方式等従来のチップオンボード法によ
っては接続することが不可能である液晶ディスプレイの
ようなガラス板に１ＴＯ膜等によって回路を形成した回
路板であってもよい。
また前記ゴムバンプはＩＣチップに設けてもＰＣＢ板に
設けてもよいが、ＩＣチップのボンディング・パッドと
の位置合せが必要とされるのでＩＣチップに設ける方が
好ましい。このゴムバンプの形成は、例えばボンディン
グ・パラにの作られているＩＣチップの表面に硬化後に
ゴム弾性を示すようになる上記した導電性ゴム組成物を
含有する導電性インクを塗布したのち、この上にボンデ
ィング・パッドの配置と同様の開口部を有するニッケル
板、ステンレス板等の金属板からなるマスク板をボンデ
ィング・パッドに位置合せして重ね、ついでこのマスク
板の開口部をキセノンランプ、ハロゲンランプなどでス
ポット加熱するか、この開口部に水銀ランプ等からの紫
外線をスポット照射してこの開口部に面した導電性イン
ク層を硬化させ、つぎにこのマスク板を取り外してボン
ディング・パッドと接していない部分の未硬化導電性イ
ンク層を溶剤を用いて溶解除去するか、あるいはＩＣチ
ップの表面に位置合せして重ねたマスク板開口部に上記
した導電性インクをスクリーン印刷し、マスク板を取外
して導電性インクを硬化または乾燥してもよい。この方
法によれば導電性のゴムバンプをボンディング・パッド
上に容易かつ確実に形成することができる。
上記した導電性インクは、ネオブレンゴム、イソプレン
ゴム、ブチルゴムなどの合成ゴム、または天然ゴム、更
には室温硬化性架橋密度のシリコーンゴム、また、スチ
レン系、ポリエステル系。
ポリオレフィン系、ポリウレタン系の各種熱可塑性エラ
ストマー等、可撓性をもたせるために長鎖の脂肪族型と
したエポキシ系等の樹脂をバインダーにし、金、銀、銅
、ニッケルなどの金属粉またはこれらの合金粉、ケッチ
ェンブラック、グラファイト等のカーボン質等の導電粉
、あるいは表面を金やニッケル等で金属めっきしたガラ
スピーズ等を導電性付与剤として１０〜６０容量％添加
したものから作られたものとすればよいが、これに更に
公知の有機過酸化物、酸無水物、アミン等の硬化剤、ま
たこれらのゴム成分をプラスチック、金属、ガラス等に
接着するためのプライマー組成物、紫外線増感剤、光開
始剤、老化防止剤、酸化防止剤などを添加したものとす
るのが好ましい。
（実施例） 室温硬化性シリコーンゴム１００部に、シランカップリ
ング剤で表面処理した平均粒径３−の銀粉を４５０部混
台分散させて作った導電性インクを、厚さ１０即となる
ようＩＣチップの表面に塗布し、この上にＩＣチップの
ボンディング・パッドと同一形状、同一パターンに開口
部を有するニッケル板によるマスク材をボンディング・
パッドと位置合せして重畳し、この開口部をキセノンラ
ンプを使用して１２０℃にまで加熱させたのちマスク板
を取外し、導電性インクの未硬化部分をトルエンを用い
て洗浄して溶解除去したところ、ＩＣチップのボンディ
ング・パッド部に、ゴム弾性をもつゴムバンプの設けら
れたＩＣチップが得られた。つぎに回路を形成した銅張
ガラス布基材エポキシ樹脂積層板の配線基板の電極に、
ＩＣチップのゴムバンプを圧接し、ついで全体を紫外線
硬化型のエポキシ樹脂によって封止して半導体装置を完
成したところ、従来法の一つであるワイヤボンディング
方式によるものと同等の電気的特性を示しながらも、作
業時間が短縮され、かつ、実装面積はおよそ１／４にな
った。
（発明の効果） 以上のように本発明の装置は、ＩＣチップと配線基板の
接続が簡単で作業時間が短縮されるにもかかわらず、高
い信頼性が得られしかも薄型化が可能で、産業上きわめ
て大きな利便を得ることが
【図面の簡単な説明】
第１図は本発明の半導体装置の縦断面図、第２図は従来
公知のＩＣチップの平面図、第３〜５図は従来公知のＩ
Ｃチップの実装技術を示す縦断面図で、第３図はワイヤ
ボンディング方式、第４図はフリップチップ方式、第５
図はＴＡＢ方式を示したものである。 １　・Ｉ　Ｃチップ、　　２・・・アクティブエリア、
３・・・入出力端子、　４・・・配線基板、５・・・電
極、　６・・・導線、　７・・・半田電極、８・・・ポ
リイミドフィルム、　　９・・・導線、１０・・・導電
性突状体、　１１・・・樹脂。 特許出願人　　　信越ポリマー株式会社１Ｓ−ミニ“−
１ ご＝　　１１（□ ）　　７・　５ ４′ 第５図

Claims (1)

  1. 【特許請求の範囲】 １）半導体集積回路チップの入出力端子と配線基板の電
    極とが弾性を有する導電性突状体を介して接続されてな
    ることを特徴とする半導体装置。 ２）導電性突状体が導電性シリコーンゴムで作られたも
    のである特許請求の範囲第１項記載の装置。 ３）導電性突状体が、半導体集積回路チップの表面に、
    硬化後にゴム状弾性体となる導電性インキを塗布し、入
    出力端子部分のインキを選択的に硬化させ、未硬化のイ
    ンキを溶解除去することによって形成されたものである
    特許請求の範囲第１項記載の装置。
JP61299639A 1986-12-15 1986-12-15 半導体装置 Pending JPS63150930A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61299639A JPS63150930A (ja) 1986-12-15 1986-12-15 半導体装置
US07/391,412 US4970780A (en) 1986-12-15 1989-08-09 Method for the assemblage of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61299639A JPS63150930A (ja) 1986-12-15 1986-12-15 半導体装置

Publications (1)

Publication Number Publication Date
JPS63150930A true JPS63150930A (ja) 1988-06-23

Family

ID=17875190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61299639A Pending JPS63150930A (ja) 1986-12-15 1986-12-15 半導体装置

Country Status (2)

Country Link
US (1) US4970780A (ja)
JP (1) JPS63150930A (ja)

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JP2625654B2 (ja) * 1995-04-28 1997-07-02 日本電気株式会社 半導体装置およびその製造方法
DE29510947U1 (de) * 1995-07-06 1995-09-14 Stocko Metallwarenfabriken Henkels Und Sohn Gmbh & Co, 42327 Wuppertal Kontaktfeldbaugruppe zur Anordnung auf einer Kontaktiereinheit
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
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US5922514A (en) 1997-09-17 1999-07-13 Dale Electronics, Inc. Thick film low value high frequency inductor, and method of making the same
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