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JPS63128736A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS63128736A
JPS63128736A JP61274173A JP27417386A JPS63128736A JP S63128736 A JPS63128736 A JP S63128736A JP 61274173 A JP61274173 A JP 61274173A JP 27417386 A JP27417386 A JP 27417386A JP S63128736 A JPS63128736 A JP S63128736A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
substrate
semiconductor
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61274173A
Other languages
Japanese (ja)
Inventor
Yoshiro Nishimura
芳郎 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP61274173A priority Critical patent/JPS63128736A/en
Publication of JPS63128736A publication Critical patent/JPS63128736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To dispose a plurality of semiconductor chips in three dimensions on a loading substrate and to decrease a required area per one chip so that chip board composition of high mounting density can be realized, by fixing a first semiconductor chip on a loading substrate and disposing a second semiconductor chip in three dimensions on the first semiconductor chip and connecting the respective semiconductor chips with respective conductive patterns on the loading substrate and sealing the respective semiconductor chips. CONSTITUTION:A first semiconductor chip 2 is fixed on a loading substrate 1, which consists of ceramics and glass-epoxy resin and the like, by die bonding. Bonding pads of the chip 2 are connected with conductive patterns, which are formed on the loading substrate 1, by the use of bonding wires 3, and next a cap 4 is put and sticked on the substrate 1 so as to seal the substrate 1. Bonding pads of a second semiconductor chip 5 fixed on the cap 4 are connected with the conductive patterns on the substrate 1 by the use of bonding wires 6. Sealing resin of a polyimide group is potted to entirely seal the cap 4, which seals the first semiconductor chip 2, and the second semiconductor chip 5 mounted on the cap 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体チップを搭載基板上に接続固定して
なる、チップオンボード構成の半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element having a chip-on-board configuration in which a semiconductor chip is connected and fixed on a mounting substrate.

〔従来の技術〕[Conventional technology]

従来のチップオンボード（Ｃ，Ｏ，Ｂ）構成の半導体素
子は、第８図＾、田）に示すように、セラミックやガラ
ス・エポキシ樹脂などからなる基板２１上に、半導体チ
ップ２２を直接ダイボンドにより固着し、該半導体チッ
プ２２のボンディングバンドと前記基板２１上に形成し
た導電パターンとをボンディングワイヤ２３で接続した
のち、封止樹脂２４あるいはキャップ２５で封止を行っ
ている。また基板２１上には必要に応じ他のチップ部品
２６が搭載されている。A conventional semiconductor device with a chip-on-board (C, O, B) configuration is produced by directly die-bonding a semiconductor chip 22 onto a substrate 21 made of ceramic, glass, epoxy resin, etc., as shown in FIG. After the bonding band of the semiconductor chip 22 and the conductive pattern formed on the substrate 21 are connected with a bonding wire 23, sealing is performed with a sealing resin 24 or a cap 25. Further, other chip components 26 are mounted on the substrate 21 as required.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、従来のチップオンボード構成の半導体素子は
、基板上に半導体チップを１個づつ平面的に配置してい
るため、多数の半導体チップを基板上に搭載する場合は
、半導体チップ数分の面積を必要とし、高実装密度が得
られないという問題点があった。However, in conventional semiconductor devices with a chip-on-board configuration, one semiconductor chip is arranged flat on a substrate, so when mounting a large number of semiconductor chips on a substrate, the area corresponding to the number of semiconductor chips is required. The problem was that high packaging density could not be obtained.

本発明は、従来のチップオンボード構成の半導体素子の
かかる問題点を解決するためなされたもので、高実装密
度を有するチップオンボード構成の半導体素子を提供す
ることを目的とするものである。The present invention has been made to solve the problems of conventional semiconductor devices with a chip-on-board configuration, and it is an object of the present invention to provide a semiconductor device with a chip-on-board configuration that has a high packaging density.

〔問題点を解決するための手段及び作用〕上記問題点を
解決するため、本発明は、搭載基板に第１の半導体チッ
プをダイボンドにより固着し、該第１の半導体チップ上
に第２の半導体チップを立体的に配置して、各半導体チ
ップをそれぞれ搭載基板上の導電パターンに接続すると
共に、各半導体チップを封止して半導体素子を構成する
ものである。[Means and effects for solving the problems] In order to solve the above problems, the present invention fixes a first semiconductor chip to a mounting substrate by die bonding, and attaches a second semiconductor chip onto the first semiconductor chip. Chips are arranged three-dimensionally, each semiconductor chip is connected to a conductive pattern on a mounting substrate, and each semiconductor chip is sealed to form a semiconductor element.

このように構成することにより、２個の半導体チップを
立体的に実装され、１チツプ当たりの実装面積の縮小化
が計れ、高密度実装が可能となる。With this configuration, two semiconductor chips can be mounted three-dimensionally, the mounting area per chip can be reduced, and high-density mounting can be achieved.

〔実施例〕〔Example〕

以下実施例について説明する。第１図は、本発明に係る
半導体素子の第１実施例を示す断面図である。この実施
例は、セラミックやガラス・エポキシ樹脂等からなる搭
載基板１に第１の半導体チップ２をダイボンドにより固
着し、該チップ２のボンディングバンドと前記搭載基板
１上に形成した導電パターンをボンディングワイヤ３を
用いて接続したのちセラミック、ガラスエポキシ樹脂な
どからなるキャップ４を被せて基板ｌに接着し、封止を
行う。Examples will be described below. FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. In this embodiment, a first semiconductor chip 2 is fixed to a mounting substrate 1 made of ceramic, glass, epoxy resin, etc. by die bonding, and a bonding band of the chip 2 and a conductive pattern formed on the mounting substrate 1 are connected using bonding wires. 3, and then a cap 4 made of ceramic, glass epoxy resin, etc. is placed on the cap 4 and bonded to the substrate 1 for sealing.

次いで前記キャップ４上に第２の半導体チップ５をダイ
ボンドにより固着し、該第２半導体チフブ５のポンディ
ングパッドと基板１上の導電パターンとをボンディング
ワイヤ６で接続し、最後にエポキシ、ポリイミド、シリ
コン系などの封止樹脂を、第１半導体チップ２を封止し
たキャップ４及びその上に載置した第２半導体チップ５
の全体を封止するようにボッティングして封止部７を形
成し、チップオンボード構成の半導体素子を構成する。Next, the second semiconductor chip 5 is fixed on the cap 4 by die bonding, the bonding pad of the second semiconductor chip 5 and the conductive pattern on the substrate 1 are connected with a bonding wire 6, and finally, epoxy, polyimide, A cap 4 sealing the first semiconductor chip 2 with a sealing resin such as silicone and a second semiconductor chip 5 placed thereon.
A sealing portion 7 is formed by botting so as to seal the entire portion, thereby configuring a semiconductor element having a chip-on-board configuration.

８は基板ｌ上に接続固定した他のチップ部品である。8 is another chip component connected and fixed on the substrate l.

このように構成することにより、１個の半導体チップ取
付面積に対して２個の半導体チップを搭載することがで
き、高実装密度が得られる。With this configuration, two semiconductor chips can be mounted on one semiconductor chip mounting area, resulting in high packaging density.

第２図は、本発明の第２実施例を示す断面図である。こ
の実施例は、第１図に示した実施例における封止樹脂の
ボッティングにより形成した封止部７で第２半導体チッ
プを封止する代わりに、キャンプを用いて封止したもの
である。すなわち、図示のように、第１半導体チフブ２
を封止したキャンプ４と、該キャップ４上にグイボンデ
ィングして載置した第２半導体チップ５とに第２のキャ
ンプ９を被せて基板ｌに接着し、これらを一体的に封止
するものである。FIG. 2 is a sectional view showing a second embodiment of the present invention. In this embodiment, instead of sealing the second semiconductor chip with the sealing portion 7 formed by botting the sealing resin in the embodiment shown in FIG. 1, the second semiconductor chip is sealed using a camp. That is, as shown in the figure, the first semiconductor chip 2
A second camp 9 is placed over the sealed camp 4 and the second semiconductor chip 5 placed on the cap 4 by bonding and bonded to the substrate l, and these are integrally sealed. It is.

第３図は、本発明の第３実施例を示す断面図である。こ
の実施例は搭載基板１に第１の半導体チップ２をダイボ
ンドで固着し、該チップ２のポンディングパッドと搭載
基板ｌ上に形成した導電パターンとをボンディングワイ
ヤ３で接続したのち、封止樹脂をボッティングして封止
部ｌＯを形成する。FIG. 3 is a sectional view showing a third embodiment of the present invention. In this embodiment, a first semiconductor chip 2 is fixed to a mounting substrate 1 by die bonding, a bonding pad of the chip 2 and a conductive pattern formed on the mounting substrate 1 are connected with a bonding wire 3, and then a sealing resin is A sealing portion IO is formed by botting.

なお、このボッティングによる封止部１０を形成する際
、上面がほぼ平面状になるように形成する。In addition, when forming the sealing part 10 by this botting, it is formed so that the upper surface is substantially planar.

次いでボッティング封止部ｌＯの上面に第２半導体チッ
プ５をダイボンドにより固着したのち、該チップ５のポ
ンディングパッドと基板１の導電パターンとをボンディ
ングワイヤ６で接続し、更に第１半導体チップ２に施し
た封止部１０と、前記第２半導体チップ５とを一体的に
封止するように、封止樹脂をボッティングして封止部１
１を形成し、半導体素子を構成するものである。Next, after fixing the second semiconductor chip 5 to the upper surface of the botting sealing part 10 by die bonding, the bonding pad of the chip 5 and the conductive pattern of the substrate 1 are connected with the bonding wire 6, and then the first semiconductor chip 2 The sealing resin is potted to integrally seal the sealing portion 10 applied to the sealing portion 1 and the second semiconductor chip 5.
1 and constitutes a semiconductor element.

第４図は、本発明の第４実施例を示す断面図である。こ
の実施例は、上記各実施例と同様に、搭載基板１に第１
半導体チップ２をダイボンドにより固着し、該チップ２
のボンディングバンドと基板１の導電パターンとをボン
ディングワイヤ３で接続したのち、このボンディングワ
イヤ３を含めた第１半導体チンブ２より若干大きい内側
面積を有し、且つ第１半導体チフブ２より若干高さを大
に形成した四角形状の枠を、第１半導体チＶブ２を囲む
ように基板１上に載置して接着する。FIG. 4 is a sectional view showing a fourth embodiment of the present invention. In this embodiment, similarly to each of the above embodiments, a first
The semiconductor chip 2 is fixed by die bonding, and the chip 2 is
After connecting the bonding band and the conductive pattern of the substrate 1 with the bonding wire 3, the bonding band has a slightly larger inner area than the first semiconductor chip 2 including the bonding wire 3, and has a slightly higher height than the first semiconductor chip 2. A rectangular frame having a large size is placed on the substrate 1 so as to surround the first semiconductor chip 2 and bonded.

次いで該枠１２上に第２半導体チップ５をダイボンドに
より接着し、該チップ５と基板１とをボンディングワイ
ヤ６で接続したのち、前記枠１２及び第２半導体チフプ
５を含めて封止するように封止樹脂をポツティングして
封止部１３を形成する。Next, the second semiconductor chip 5 is bonded onto the frame 12 by die bonding, and the chip 5 and the substrate 1 are connected with bonding wires 6, and then the frame 12 and the second semiconductor chip 5 are sealed together. A sealing portion 13 is formed by potting a sealing resin.

この実施例では封止工程が一回で済むという利点がある
。This embodiment has the advantage that only one sealing step is required.

第５図は、本発明の第５実施例を示す断面図である。こ
の実施例では搭載基板１に第１半導体チップ２をダイボ
ンドにより固着して、該チップ２と基板１の導電パター
ンとをボンディングワイヤ３で接続したのち、第１半導
体チップ２の上面に、ボンディングワイヤ３に接触しな
いように、チ、２プ載置幅広面１４′を有する絶縁性台
板１４を接合し、咳台板１４の幅広面１４′に第２半導
体チップ５をダイボンドにより接合し、第２半導体チッ
プ５と基板１とをボンディングワイヤ６により接続した
のち、第１半導体チンプ２及び第２半導体チップ５を共
通に封止するように封止樹脂をポツティングして封止部
１５を形成する。このように構成した場合も一回の封止
工程により封止部を形成することができる。FIG. 5 is a sectional view showing a fifth embodiment of the present invention. In this embodiment, a first semiconductor chip 2 is fixed to a mounting board 1 by die bonding, and the chip 2 and the conductive pattern of the board 1 are connected with a bonding wire 3. An insulating base plate 14 having a wide chip mounting surface 14' is bonded so as not to contact the chips 3, and a second semiconductor chip 5 is bonded to the wide surface 14' of the cough base plate 14 by die bonding. After the two semiconductor chips 5 and the substrate 1 are connected by bonding wires 6, a sealing resin is potted to commonly seal the first semiconductor chip 2 and the second semiconductor chip 5 to form a sealing part 15. . Even with this configuration, the sealing portion can be formed by a single sealing process.

第６図は、本発明の第６実施例を示す断面図である。こ
の実施例は、第１図に示した実施例と同様に第１半導体
チップ２に封止用キャンプ４を被せたのち、該キャンプ
４上に該キャップ４とほぼ同一の外形を有するワイヤシ
ョート防止用枠１６を接着する０次いで該封止用キャン
プ４の上面に第゛　２半導体チフブ５をダイボンドで接
着したのち、該チップ５のポンディングパッドと基板ｌ
の電極パターンとをボンディングワイヤ６で接続する。FIG. 6 is a sectional view showing a sixth embodiment of the present invention. In this embodiment, similarly to the embodiment shown in FIG. 1, a sealing camp 4 is placed over the first semiconductor chip 2, and then a wire short-circuit preventive device is placed on the camp 4 to prevent wire short-circuiting. Next, the second semiconductor chip 5 is bonded to the upper surface of the sealing camp 4 by die bonding, and then the bonding pad of the chip 5 and the substrate l are bonded.
are connected to the electrode pattern using bonding wires 6.

この際ボンディングワイヤ６はワイヤショート防止用枠
１６で支持されるように配設される０次いでキャンプ４
及び第２半導体チフプ５及び枠１６の全体を封止するよ
うに封止用樹脂をポツティングして封止部１７を形成す
る。At this time, the bonding wire 6 is supported by the wire short-circuit prevention frame 16.
Then, a sealing resin is potted to seal the entire second semiconductor chip 5 and frame 16, thereby forming a sealing portion 17.

一般に２つの半導体チップを立体的に配置した場合高さ
が高くなり、したがって第２チツプのポンディングパッ
ドと基板の導電パターンとを接続するボンディングワイ
ヤの長、さが長くなり、該ワイヤとチンプエッジ間のシ
ョートが発生しやすくなるが、この実施例では、第２半
導体チップ５のポンディングパッドへ接続されるボンデ
ィングワイヤ６は、ワイヤショート防止用枠１６で保持
されているため、上記ワイヤショートの発生を有効に防
止することができる。Generally, when two semiconductor chips are arranged three-dimensionally, the height becomes high, and therefore the length of the bonding wire that connects the bonding pad of the second chip and the conductive pattern of the substrate becomes long, and the distance between the wire and the chimp edge increases. However, in this embodiment, since the bonding wire 6 connected to the bonding pad of the second semiconductor chip 5 is held by the wire short prevention frame 16, the occurrence of the wire short is likely to occur. can be effectively prevented.

第７図は、本発明の第７実施例を示す断面図である。こ
の実施例は、第３図に示した第３実施例のように、搭載
基板１に第１半導体チップ２をダイボンドにより固着し
、該チップ２のポンディングパッドと基板１上に形成さ
れた導電パターンとをボンディングワイヤ３で接続した
のち、封止樹脂をポツティングして封止部１０を形成す
る。FIG. 7 is a sectional view showing a seventh embodiment of the present invention. In this embodiment, as in the third embodiment shown in FIG. After connecting the pattern with the bonding wire 3, a sealing resin is potted to form a sealing portion 10.

次に、この封止部ｌＯの２倍以上の高さを有し、上板１
８’の内面の一部から側板１８′の内面を通り、該側板
１８＃の外面下端部に到る所定の導電パターン１９を形
成したキャップ１８の上板１８′の内面に第２半導体チ
ップ５をダイボンドにより接着し、該チップ５のポンデ
ィングパッドとキャップ１８の内面に形成した導電パタ
ーン１９とをボンディングワイヤ６で接続する０次にこ
のように構成したキャップ１８を、前記第１半導体チッ
プ２を封止した封止部１０上に被せて基板１に接着する
と共に、キャップ１８の側板１８“の外面底部に形成さ
れている導電パターン１９と基板１に形成されている導
電パターンとをハンダ２０等により接続し、半導体素子
を構成するものである。Next, the upper plate 1 has a height more than twice that of this sealing part lO.
A second semiconductor chip 5 is disposed on the inner surface of the upper plate 18' of the cap 18, on which a predetermined conductive pattern 19 is formed from a part of the inner surface of the cap 18, passing through the inner surface of the side plate 18' and reaching the lower end of the outer surface of the side plate 18#. The bonding pad of the chip 5 and the conductive pattern 19 formed on the inner surface of the cap 18 are connected by a bonding wire 6. The conductive pattern 19 formed on the bottom of the outer surface of the side plate 18'' of the cap 18 and the conductive pattern formed on the substrate 1 are bonded together using solder 20. etc., to form a semiconductor element.

本発明は、上記各実施例に示したものに限らず、例えば
上記各実施例に示した第１半導体チップ及び第２半導体
チップに対する封止手段あるいはそれら支持手段等は適
宜組み合わせることができる。The present invention is not limited to what is shown in each of the above embodiments, and for example, the sealing means for the first semiconductor chip and the second semiconductor chip or their supporting means shown in each of the above embodiments can be combined as appropriate.

〔発明の効果〕〔Effect of the invention〕

以上実施例に基づいて説明したように、本発明によれば
、複数個の半導体チップを搭載基板上に立体的に配設し
たので、１チツプ当たりの所要面積を減少させ、高実装
密度のチップオンボード構成の半導体素子を得ることが
できる。As described above based on the embodiments, according to the present invention, a plurality of semiconductor chips are arranged three-dimensionally on a mounting board, which reduces the required area per chip and allows for high packaging density. A semiconductor device with an on-board configuration can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第７図は、それぞれ本発明の第１乃至第７実
施例を示す断面図、第８図は＾、　（Ｂ）は、従来のチ
ップオンボード構成の半導体素子の構成例を示す断面図
である。 図において、ｌは搭載基板、２は第１半導体チップ、３
．６はボンディングワイヤ、４．９はキャップ、５は第
２半導体チップ、７．１０．１１．１３゜１５、１７は
封止部、８はチップ部品、１２は枠、１４は合板、１６
はワイヤショート防止用枠、１８はキャップ、１９は導
電パターン、２０はハンダを示す。 特許出願人　オリンパス光学工業株式会社代理人弁理士
　　最　　上　　健　　治７２１５、第１図 第２図 第３図 第４図 第５図 第６図1 to 7 are cross-sectional views showing the first to seventh embodiments of the present invention, respectively, and FIG. 8 is a cross-sectional view showing an example of the structure of a semiconductor element having a conventional chip-on-board structure. FIG. In the figure, l is a mounting board, 2 is a first semiconductor chip, and 3 is a mounting board.
．． 6 is a bonding wire, 4.9 is a cap, 5 is a second semiconductor chip, 7.10.11.13° 15, 17 is a sealing part, 8 is a chip component, 12 is a frame, 14 is a plywood board, 16
18 indicates a wire short prevention frame, 18 a cap, 19 a conductive pattern, and 20 a solder. Patent applicant Olympus Optical Industry Co., Ltd. Patent attorney Kenji Mogami 7215, Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 　搭載基板に第１の半導体チップをダイボンドにより固
着し、該第１の半導体チップ上に第２の半導体チップを
立体的に配置して、各半導体チップをそれぞれ搭載基板
上の導電パターンに接続すると共に、各半導体チップを
封止したことを特徴とする半導体素子。A first semiconductor chip is fixed to a mounting board by die bonding, a second semiconductor chip is three-dimensionally arranged on the first semiconductor chip, and each semiconductor chip is connected to a conductive pattern on the mounting board, respectively. , a semiconductor element characterized in that each semiconductor chip is sealed.
JP61274173A 1986-11-19 1986-11-19 Semiconductor element Pending JPS63128736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61274173A JPS63128736A (en) 1986-11-19 1986-11-19 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61274173A JPS63128736A (en) 1986-11-19 1986-11-19 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS63128736A true JPS63128736A (en) 1988-06-01

Family

ID=17538052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61274173A Pending JPS63128736A (en) 1986-11-19 1986-11-19 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS63128736A (en)

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US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
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US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US5856915A (en) * 1997-02-26 1999-01-05 Pacesetter, Inc. Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity
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US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
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US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
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US7126218B1 (en) 2001-08-07 2006-10-24 Amkor Technology, Inc. Embedded heat spreader ball grid array
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
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US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
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US20160379933A1 (en) * 2007-02-21 2016-12-29 Amkor Technology, Inc. Semiconductor package in package
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