JPH03109760A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance packaging density of semiconductor chips to a package by superposing a plurality of semiconductor chips mutually so that an electrode for external connection which are formed on the same surface may be exposed in the same surface direction. CONSTITUTION:Semiconductor chips 4 and 8 are mutually superposed so that electrodes 5 and 9 for external connection which are formed on the same plane in respective semiconductor chip 4 and 8 may be exposed in the same surface direction. Namely, all the electrodes for external connection 5 of the chip 4 are formed on the upper surface as the same surface, are exposed toward the upper side as the same surface direction, are placed at both edge parts on the upper surface of the chip 4 along the X-direction, and are connected to an inner lead 7 by a wire 6. Also, the electrode 9 for all the external connection of the chip 8 is formed on the upper surface as the same surface and are placed along the Y-direction. Thus, it is not covered by a die pad 3 and a chip 4 and are exposed toward the upper side as the same surface direction and are connected to the inner lead 7, thus enhancing the packaging density to the package 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a structure in which a semiconductor chip is mounted in a package.

[Prior Art] As a semiconductor device having a structure in which a semiconductor chip is mounted in a package, devices using a dual-in-line package, a flat package, a chip carrier, a film carrier, etc. are known.

In such semiconductor devices, it is generally desired that semiconductor chips be mounted with higher density. Therefore,
In order to mount semiconductor chips at a higher density, a semiconductor device has been proposed that has a structure in which a plurality of semiconductor chips are arranged and mounted in a planar manner in one package.

According to the semiconductor device, since a plurality of semiconductor chips are arranged in a plane, inner lead bonding (electrical connection between the inner lead of the package and the electrode for external connection of the semiconductor chip) is performed when mounting the semiconductor chips. The process (connection) can be carried out using the same bonding technology as in the case of mounting a single conventional semiconductor chip, and therefore has the advantage of being easy to manufacture.

[Problems to be Solved by the Invention] However, in the conventional semiconductor device described above, which has a structure in which a plurality of semiconductor chips are mounted, the plurality of semiconductor chips are arranged in a plane, so that there are limited The total base area of semiconductor chips that can be mounted in a package with a base area is limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has a high packaging density of semiconductor chips in a package and is easy to manufacture.

[Means for Solving the Problems] According to the present invention, the object is to provide a plurality of external connection electrodes formed on the same surface, and overlap each other so that the electrodes are exposed in the same surface direction. This is achieved by a semiconductor device comprising a plurality of semiconductor chips and a package in which the plurality of semiconductor chips are mounted.

[Operation] According to the semiconductor device of the present invention, since a plurality of stacked semiconductor chips are mounted in a package, the total base area of the semiconductor chips that can be mounted in the package having a limited base area can be reduced by This can be at least twice as large as in the case of a conventional semiconductor device in which a plurality of semiconductor chips are mounted. Since a plurality of semiconductor chips are stacked on top of each other so that a plurality of external connection electrodes formed on the same surface of each semiconductor chip are exposed in the same surface direction, the inner layer in manufacturing the semiconductor device of the present invention is The lead bonding process can be easily performed by connecting the inner leads of the package and the electrodes for external connection using a wire bonding technique or a wireless bonding technique from the same plane. As a result, in the semiconductor device of the present invention, the packaging density of semiconductor chips in a package can be increased, and manufacturing can be facilitated.

These effects of the present invention will become clearer from the following examples of the present invention, and other effects of the present invention will become clearer.

[Example code] Embodiments of the present invention will be described based on the drawings.

A semiconductor device 1, which is an embodiment of the present invention, is shown in FIG. 1 as a plan perspective view and FIG. 2 as a sectional view taken along line II' in FIG. The package body 2 is made of molded resin. That is, the semiconductor device 1 is comprised of a dual-in-line package of resin mold type.

The lower surface of a semiconductor chip 4 is firmly bonded to the upper surface of a die pad 3 made of metal using an adhesive.

As the adhesive, an adhesive made of silver, epoxy, or the like is preferable. All the electrodes 5 for external connection of the chip 4 are formed on the same upper surface, are exposed toward the upper side of the same surface, and are arranged on both edges of the upper surface of the chip 4 along the X direction. ing. The electrode 5 is connected by a wire 6 to an inner lead 7 made of metal.

The upper surface of the semiconductor chip 8 is firmly bonded to the lower surface of the die pad 3 with a heat-resistant insulating film 12 .

As can be seen from the plan view of FIG. 1, the chip 8 is longer than the chip 4 in the X direction, and the chip 8 has a plane at both ends in the X direction that can be seen from above without being hidden by the die pad 3 and the chip 4 in FIG. It has a shape. All of the external connection electrodes 9 of the chip 8 are formed on the same upper surface at both ends and are arranged along the Y direction.

Therefore, the electrode 9 is not covered by the die pad 3 and the chip 4 and is exposed upward in the same plane direction, and is connected to the inner lead 7 by the wire 10. The insulating film 12 is made of polyimide or the like.
A film having a thickness of 0 μm to 100 μm is preferred. By providing the insulating film 12, it is possible to prevent electrical short circuits caused by minute scratches that may exist on the bonding surfaces of the chips 4 and 8.

The die pad 3, inner leads 7, chips 4 and 8, wires 6 and 10, and insulating film 12 are connected to the package body 2.
The inside is sealed with resin. The outer lead 11 made of metal and integral with the inner lead 7 protrudes outside the package body 2, and is soldered to wiring provided on a substrate (not shown) to which the semiconductor device 1 is attached by a technique or a thermocompression bonding technique. electrically connected. Note that the die pad 3 may or may not be connected to the outer lead 11 for grounding.

A method for manufacturing the semiconductor device 1 of this embodiment will be described below.

First, Gui Pad 3, Inner Lead 7, Outer Lead 1
A monolithic metal lead frame is provided that includes a lead frame 1 and an outer frame portion.

Next, the semiconductor chip 4 is firmly bonded to the upper surface of the die pad 3 with an adhesive, and the semiconductor chip 8 is firmly bonded to the lower surface of the die pad 3 using an insulating film 12.

Next, in a dedicated wire bonding connection device,
The lead frame and chip 8 are held down from the lower side, which is the side opposite to the side to which the inner leads 7 are to be connected. The electrode 5 is connected to the inner lead 7 from above by a wire 6 using a well-known wire bonding technique. On the other hand, the electrodes 9 are arranged facing upward at both ends of the chip 8, and are exposed without being covered by the die pad 3 and the chip 4 in the plan view. It is easily connected to the inner lead 7 by the wire 18 from above in the same manner as in the above case.

Next, the die pad 3, inner leads 7, chips 4 and 8, wires 6 and 10 . Further, the insulating film 12 is set in a molding device and filled with resin, and the resin is cured by heat treatment or the like and sealed within the package body 2.

Next, the outer frame portion of the lead frame is cut and the outer lead 11 is bent to obtain the semiconductor device 1.

In this embodiment, the chips 4 and 8 may be the same type of elements or may be different types of elements.

If the chips 4 and 8 are both memory elements, the amount of memory per bottom area of the package body 2 can be reduced by about 2 compared to the conventional method.
Can be doubled.

In particular, the chip 4 is a solid-state imaging device such as a CCD, the chip 8 is an IC for processing an imaging signal, the package body 2 is made of transparent resin, and the chips 4 and 8 are separated within the package body 2. If a suitable wiring pattern of the inner leads 7 and/or wire wiring between the inner leads 7 is provided, the semiconductor device 1 can be a device having an imaging function and a signal processing function at the same time. In this case, the length of the wiring between the solid-state image pickup device and the signal processing IC can be very short, so there is an advantage that the time required for signal processing can be particularly reduced. Furthermore, in this case, since the die pad 3 can have a function as a light shielding plate for the signal processing IC, the semiconductor device 1
It is advantageous in terms of its structure. In this way, in this embodiment, by devising a combination of the chips 4 and 8, which are different types of elements, effects that cannot be obtained when the chips 4 and 8 are the same type of elements can be obtained.

In the above embodiment, the electrodes 5 and 9 are connected to the inner lead 7 by wire bonding technology.
Tabs, bumps, etc. may be provided on the inner lead 7 or on the electrodes 5 and 9, and the electrodes 5 and 9 may be connected to the inner lead 7 by a wireless bonding technique using thermocompression bonding, soldering, or the like. Furthermore, if the connection by wireless bonding technology is used in this way, even if the electrodes 9 of the lower chip 8 are hidden by the upper chip 4 in the plan view of FIG. If a small die pad 3 is used and configured so that a gap is formed between the chips 4 and 8 due to the thickness of the die pad 3, and the electrode 9 is exposed to the gap at the end of the upper surface of the chip 8, the gap can be filled. There is an advantage that the electrode 9 and the inner lead 7 can be connected by inserting the tip of the inner lead 7.

In the above embodiment, the electrode 5 is arranged at the edge of the chip 4 along the X direction, and the electrode 9 is arranged at the end of the chip 8 along the Y direction. The electrodes 5 may be arranged at the edges of the chip 8 along the Y direction, and the electrodes 5 may be arranged at the ends of the chip 4 along the Y direction. Further, a part of the electrode 5 may be arranged at the edge of the chip 4 along the X direction, and another part of the electrode 5 may be arranged at the end of the chip 4 along the Y direction. Furthermore, both electrodes 5 and 9 may be located along the edges of chips 4 and 8 along the X direction, and both electrodes 5 and 9 may be located along the edges of chips 4 and 8 along the Y direction. It may be placed in the section. If one end or one edge is shared by the electrodes 5 and 9, the wires 6 and 10 may be arranged in an alternating manner, or may be arranged in a suitable length. One area may be allocated to the electrode 5, and another area of an appropriate length may be allocated to the electrode 9. In any of the embodiments, in order to easily connect the electrode 9 and the inner lead 7 during the manufacturing process, the planar shape of the chips 4 and 8 and the guide pad 3 is such that the electrode 9 can be seen in the plan view of FIG. Preferably, a combination is selected.

Furthermore, it is preferable to select the arrangement of the electrodes 5 and 9 and the inner lead 7 so that the wires 6 and 10 can be connected without crossing each other.

In the above embodiment, the electrodes 5 and 9 are all on the tip 4.
and 8 are formed only on the top surface and in the same direction (upper side)
facing. Therefore, it is only necessary to perform inner lead bonding from one side (the upper side), and there is no need to turn over the lead frame during inner lead bonding. Since it is easy to hold down the lead frame and chip 8 from the side (lower side), it is practical and very advantageous in terms of manufacturing process and manufacturing cost. However, it is not necessary that all of the electrodes 5 and 9 face the same direction, and some of the electrodes 5 and 9
The other portions of the electrodes 5 and 9 may be formed on the lower surfaces of the chips 4 and 8 and face downward. In this case, avoid damaging the connection points on one side by using a special jig configured to hold the package and semiconductor chip from one side while avoiding the connection points that have already been connected on the other side. Connection can be made from the other side using wire bonding technology, wireless bonding technology, or the like while the device is pressed in this manner.

In the above embodiment, two chips 4 and 8 are mounted inside the package body 2, but three or more semiconductor chips are stacked on top of each other with an insulating film or the like interposed therebetween. It may be implemented in In this case as well, since the plurality of semiconductor chips are overlapped with each other so that the plurality of external connection electrodes formed on the same surface of each semiconductor chip are exposed in the same surface direction, the electrodes and the inner leads are The connection can be easily performed in substantially the same manner as in the case of the semiconductor device 1 described above. In this case,
If the semiconductor chips stacked below are configured to have longer lengths in the X direction and/or Y direction so that the electrodes of each chip can be seen from above, it will be easier to connect the electrodes to the inner leads. . Furthermore, even if a large number of semiconductor chips having the same shape are slightly shifted in the X direction and/or Y direction so that the electrodes of each chip can be seen from above, the electrodes and the inner leads can be easily connected. Become.

In the above embodiments, the semiconductor device 1 is mounted in a dual-in-line package of resin mold type, but it may also be a dual-in-line package of laminated ceramic type or glass ceramic type. , or a flat package, pin grid array, chip carrier, or tape carrier.

[Effects of the Invention] According to the semiconductor device of the present invention, since a plurality of stacked semiconductor chips are mounted in a package, the total base area of the semiconductor chips that can be mounted in the package having a limited base area is reduced. can be increased.

Since a plurality of semiconductor chips are stacked on top of each other so that a plurality of external connection electrodes formed on the same surface of each semiconductor chip are exposed in the same surface direction, the inner layer in manufacturing the semiconductor device of the present invention is The lead bonding process can be easily performed. As a result, according to the present invention, it is possible to provide a semiconductor device in which the packaging density of semiconductor chips in a package is increased and which is easy to manufacture.

[Brief explanation of drawings]

FIG. 1 is a plan perspective view showing one embodiment of the present invention, and FIG. 2 is a sectional view taken along line I-1' in FIG. 1...Semiconductor device, 2...Package body, 3...Guipad, 4.8...
Semiconductor chip, 5, 9...electrode, 6. 10...Wire, 7...Innalide, 11...Autaride, 12...Insulating film.

Claims (1)

[Claims] A plurality of semiconductor chips each having a plurality of external connection electrodes formed on the same surface and stacked on top of each other so that the respective electrodes are exposed in the same surface direction, and a package in which the plurality of semiconductor chips are mounted. A semiconductor device comprising: