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JPS59107551A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59107551A
JPS59107551A JP57216921A JP21692182A JPS59107551A JP S59107551 A JPS59107551 A JP S59107551A JP 57216921 A JP57216921 A JP 57216921A JP 21692182 A JP21692182 A JP 21692182A JP S59107551 A JPS59107551 A JP S59107551A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor chip
wiring
mounting board
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57216921A
Other languages
Japanese (ja)
Inventor
Hajime Sato
佐藤　始
Kenichi Otsuka
大塚　憲一
Wahei Kitamura
北村　和平
Hiromichi Suzuki
博通 鈴木
Hiroshi Mikino
三木野　博
Ryosuke Kimoto
良輔 木本
Hideki Kosaka
小坂　秀樹
Hajime Murakami
元 村上
Masachika Masuda
正親 増田
Tokuji Toida
戸井田　徳次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP57216921A priority Critical patent/JPS59107551A/en
Publication of JPS59107551A publication Critical patent/JPS59107551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に、半導体チップの実装
基板への取付構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure for attaching a semiconductor chip to a mounting board.

１つの半導体チップへの回路素子の高集積化あるいは高
密度化に伴い、半導体チップから外部に引出される配線
数が増加する。すなわち、半導体チップに設けられた多
くのポンディングパッドを介してコネクタワイヤによっ
て半導体チップ内の配線を、その外部へと引き出さなけ
ればならない。2. Description of the Related Art As circuit elements become more highly integrated or more densely integrated into one semiconductor chip, the number of wires drawn out from the semiconductor chip increases. That is, the wiring inside the semiconductor chip must be led out to the outside by connector wires through many bonding pads provided on the semiconductor chip.

この場合、半導体チップが実装されるリードフレーム、
プリント基板、セラミックパッケージ基板等の半導体チ
ップ実装基板の配線を如何に高密度に形成するかが課題
となる。この実装基板には、半導体チップに設けられる
多数のポンディングパッドに対応したポンディングパッ
ド部およびこのパッド部から実装基板のピン配置部又は
基板のターミナル部圧延在する配線部を設ける必要があ
るが、実装密度な犬ぎくするためにこれらの部分が高密
度に形成されることが要求される。In this case, the lead frame on which the semiconductor chip is mounted,
The challenge is how to form high-density wiring on semiconductor chip mounting boards such as printed circuit boards and ceramic package boards. It is necessary to provide this mounting board with a bonding pad section corresponding to a large number of bonding pads provided on the semiconductor chip, and a wiring section extending from this pad section to the pin arrangement section of the mounting board or the terminal section of the board. In order to achieve high packaging density, these parts are required to be formed at high density.

従来の実装基板に半導体チップを取付けた半導体装置と
して第４図のものが周知である。第４図にて、１は、論
理回路およびメモリなどが形成された半導体チップで、
シリコン基板から成る。２は、半導体チップの周辺部に
形成されたポンディングパッド。３は、実装基板で、半
導体チップ１な配設するための溝部４と、ポンディング
パッド部５と、そのパッド部５から延在する配線部６と
を有する。チップ側ポンディングパッド２と、基板側ホ
ンティングパッド５とはコネクタワイヤ７とによって電
気的に接続されている。As a conventional semiconductor device in which a semiconductor chip is mounted on a mounting board, the one shown in FIG. 4 is well known. In FIG. 4, 1 is a semiconductor chip on which a logic circuit, memory, etc. are formed.
Consists of a silicon substrate. 2 is a bonding pad formed on the periphery of the semiconductor chip. Reference numeral 3 denotes a mounting board, which has a groove portion 4 for arranging the semiconductor chip 1, a bonding pad portion 5, and a wiring portion 6 extending from the pad portion 5. The chip side bonding pad 2 and the substrate side bonding pad 5 are electrically connected by a connector wire 7.

この従来の実装構造においては、実装基板側のポンディ
ングパッド５としては所実の横巾（例えば０．２　ｙｎ
ｔｎ　）のものが用いられており、しかも、ボンディン
グ部５に於けるポンディングパッド相互間には必ずある
間隔（例えば０．１５１１１１１）をもたせる必要があ
る。すなわち、ボンディングバンドは所定の横巾を必要
とし、また、その相互間には所定の間隔が必要である。In this conventional mounting structure, the bonding pad 5 on the mounting board side has an actual width (for example, 0.2 yn
tn) is used, and it is necessary to provide a certain distance (for example, 0.1511111) between the bonding pads in the bonding portion 5. That is, the bonding bands require a predetermined width and a predetermined spacing between them.

しかも従来の実装基板では、第１図に示すように、ボン
ディング部５と配線部６とが、配線の長さ方向に対し均
一の幅を以って形成されている。従って、かかる実装基
板の形態にあっては多数のポンディングパッドを配する
ことができず、実装基板における多ビン化または多数の
ターミナル化をすることが困難であった。Moreover, in the conventional mounting board, as shown in FIG. 1, the bonding part 5 and the wiring part 6 are formed with a uniform width in the length direction of the wiring. Therefore, in the form of such a mounting board, it is not possible to arrange a large number of bonding pads, and it is difficult to provide a large number of bins or a large number of terminals on the mounting board.

従って、半導体チップの高集積化を図って多ビン化する
には、半導体チップの実装基板の配線構造に制約かあっ
た。Therefore, in order to increase the integration of semiconductor chips and increase the number of bins, there are restrictions on the wiring structure of the semiconductor chip mounting board.

本発明は、半導体チップの高密度化に伴って要求される
多ビン化に適した実装基板を与えることを目的とする。An object of the present invention is to provide a mounting board suitable for increasing the number of bins required as the density of semiconductor chips increases.

以下に本発明を実施例について、図面に基づいて説明す
る。The present invention will be described below with reference to the drawings.

第１図は本発明に係る半導体装置の平面構造を示し、第
２図はその断面構造を示す。第１図および第２図にて、
８は四角形の半導体チップで、シリコン単結晶基板から
成る。周知の技術によってこの半導体チップ内には多数
の回路素子が形成され、１つの回路機能を与えている。FIG. 1 shows a planar structure of a semiconductor device according to the present invention, and FIG. 2 shows its cross-sectional structure. In Figures 1 and 2,
8 is a rectangular semiconductor chip made of a silicon single crystal substrate. A large number of circuit elements are formed within this semiconductor chip using well-known techniques to provide one circuit function.

回路素子は、例えば、絶縁ゲート型電界効果トランジス
タ（ＭＯＳトランジスタ）から成り、これらの回路素子
によって、例えば論理回路およびメモリ回路機能が形成
されている。半導体チップの周辺部には、外部と電気的
結合な与えるためのボンディングバンド９が形成されて
いる。このボンディングバンドは例えばアルミニウムの
金属から構成されている。The circuit elements include, for example, insulated gate field effect transistors (MOS transistors), and these circuit elements form, for example, logic circuit and memory circuit functions. A bonding band 9 is formed around the periphery of the semiconductor chip to provide electrical connection with the outside. This bonding band is made of a metal such as aluminum.

１０は四角形の実装基板で、例えばセラミックの基板か
ら構成されている。この基板は、樹脂から構成されたプ
リント基板であっても良い。実装基板１０は、その中央
部に半導体チップ８を固着している溝部１１を有し、さ
らに、半導体チップ８のポンディングパッド９に対応し
て形成された金属のポンディングパッド部１２と、これ
らのパッド部から延在する金属の配線部１３と、配線部
に一体に接続された金属のターミナル部１４とを有する
一実装基板のポンディングパッド部、配線部およびター
ミナル部の金属層としては、セラミック基板を使用する
場合、タングステンまたはモリブテンなどを印刷技術に
よって形成されたものが使用され、また樹脂基板の場合
、銅泊が使用される。特に、ボンディング部１２には第
３図に示すように金メッキ１２′が施されている。Reference numeral 10 denotes a rectangular mounting board, which is made of, for example, a ceramic board. This board may be a printed board made of resin. The mounting board 10 has a groove part 11 in the center thereof to which the semiconductor chip 8 is fixed, and further includes a metal bonding pad part 12 formed corresponding to the bonding pad 9 of the semiconductor chip 8, and The metal layers of the bonding pad section, the wiring section, and the terminal section of one mounting board have a metal wiring section 13 extending from the pad section and a metal terminal section 14 integrally connected to the wiring section. When a ceramic substrate is used, one made of tungsten or molybdenum using a printing technique is used, and when a resin substrate is used, a copper foil is used. In particular, the bonding portion 12 is plated with gold 12' as shown in FIG.

本発明において、特に、ボンディングバラｈＪ１２およ
び配線部１３は、第３図に示すように、配線部１３をポ
ンディングパッド部１２より幅狭く形成している。配線
部１３０幅Ｙは、例えば、０．３朋に形成され、ボンテ
ィングパッド部１２０幅Ｘは０．１問に形成されている
。これらのパッド部１２ば、アルミニウムまたは金のコ
ネクタワイヤ１７によって、半導体チップのポンディン
グパッド部９に電気的接続されている。In the present invention, in particular, the bonding rose hJ12 and the wiring part 13 are formed so that the wiring part 13 is narrower than the bonding pad part 12, as shown in FIG. The width Y of the wiring portion 130 is, for example, 0.3 mm, and the width X of the bonding pad portion 120 is 0.1 mm. These pad portions 12 are electrically connected to the bonding pad portions 9 of the semiconductor chip by aluminum or gold connector wires 17.

第１図及び第２図ではポンディングパッド１２の先端部
の四隅を直角と成した例を示しであるが、円孤状等の他
の形状に構成しても差支えない。Although FIGS. 1 and 2 show an example in which the four corners of the tip of the bonding pad 12 are formed at right angles, it may be configured in other shapes such as a circular arc shape.

本発明のボンディング部１２は第１図に示すようＫ、上
記形状のポンディングパッド１２を複数個横方向に適宜
間隔を置いて配列し、当該ホンディングパッドから延在
する配線部１３０幅の狭い部分の相互間に形成された空
間１５に同じ形状のボンディングバンドを配列して成る
。As shown in FIG. 1, the bonding part 12 of the present invention has a plurality of bonding pads 12 having the above-mentioned shape arranged at appropriate intervals in the lateral direction, and a wiring part 130 extending from the bonding pad having a narrow width. Bonding bands of the same shape are arranged in spaces 15 formed between the parts.

このようにして、第１列群のポンディングパッド間のす
き間に第２列群のバンドを形成することニヨって、実装
基板に多数のボンディングバンドを収容することができ
、多ビン化が容易となる。In this way, by forming the bands of the second row group in the gaps between the bonding pads of the first row group, it is possible to accommodate a large number of bonding bands on the mounting board, and it is easy to increase the number of bins. becomes.

尚、半導体チップ８と実装基板のポンディングパッド部
１２とは、第２図に示すように樹脂層１６によって保護
される。Incidentally, the semiconductor chip 8 and the bonding pad portion 12 of the mounting board are protected by a resin layer 16 as shown in FIG.

本発明は、例えばウォッチモジュール基板（時計組立用
回路基板）に応用できる。例えば、ガラスエポキシ材料
から成る、ウォッチモジュール用基板は、そこ罠取付け
される半導体チップのために、多くのポンディングパッ
ドを必要とするが、かかる場合にあっても本発明により
多ビン化に対応した半導体装置を提供することができる
。The present invention can be applied to, for example, a watch module board (a circuit board for timepiece assembly). For example, a watch module substrate made of glass epoxy material requires many bonding pads for semiconductor chips to be mounted thereon, but even in such cases, the present invention can accommodate multiple bins. A semiconductor device can be provided.

上述の実施例では、実装基板が配線部のターミナル部で
終端したが、パッケージを構成する場合、ターミナル部
がビンに接続されてもよい。さらに、本発明は、半導体
チップを複数実装する場合の回路基板の一部に、もしく
は、他の電子部品を含む回路基板の一部に、半導体チッ
プを取付けする場合の実装構造として適用できる。また
、半導体チップ部の封止形態は、樹脂封止方式に限らず
、キャップによって保護する方式であっても良い。In the above-described embodiment, the mounting board terminates at the terminal section of the wiring section, but when configuring a package, the terminal section may be connected to the bottle. Furthermore, the present invention can be applied as a mounting structure when a semiconductor chip is attached to a part of a circuit board in which a plurality of semiconductor chips are mounted, or to a part of a circuit board that includes other electronic components. Further, the sealing form of the semiconductor chip portion is not limited to the resin sealing method, and may be protected by a cap.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は、本発明に伴う半導体装置の部分
的な平面図および断面図をそれぞれ示す。 第３図は、第１図に示したボ／メイングパッド部および
配線部の形状を説明するための略式図を示す。 第４図は従来の半導体装置を示す。 １．８・・・半導体チップ、１０・・・実装基板（セラ
ミック基板）、２．ｇ１２・・・ポンプイングツくノド
部、１３・・・配線部。 第　　１　　図 ノ／ 第　　２　図 第　　３　　図 ２ 第　　４　図 第１頁の続き ０発　明　者　小坂秀樹 小平市上水本町１４５０番地株式会 社°日立製作所武蔵工場内 ０発　明　者　村上元 小平市上水本町１４５０番地株式会 社日立製作所武蔵工場内 ０発　明　者　増田正親 小平市上水本町１４５０番地株式会 社日立製作所武蔵工場内 ０発　明　者　戸井田徳次 小平市上水本町１４５０番地株式会 社日立製作所武蔵工場内 ０出　願　人　日立マイクロコンピュータエンジニアリ
ング株式会社 小平市上水本町１４７９番地1 and 2 show a partial plan view and a sectional view, respectively, of a semiconductor device according to the present invention. FIG. 3 shows a schematic diagram for explaining the shapes of the main pad section and wiring section shown in FIG. 1. FIG. 4 shows a conventional semiconductor device. 1.8... Semiconductor chip, 10... Mounting board (ceramic board), 2. g12...Pumping throat section, 13...Wiring section. Figure 1 / Figure 2 Figure 3 Figure 2 Figure 4 Continued from page 10 Inventor: Hideki Kosaka, 1450 Kamimizu Honcho, Kodaira City, Musashi Factory, Hitachi, Ltd. 0 Inventor: Motomuramurakami, Kodaira City 1450 Mizuhonmachi, Hitachi, Ltd. Musashi Factory Inventor Masachika Masuda 1450 Kamizu Honmachi, Kodaira City Musashi Factory, Hitachi, Ltd. 0 Inventor Tokuji Toida 1450 Kamizu Honmachi, Kodaira City Musashi, Hitachi, Ltd. 0 applicants within the factory Hitachi Microcomputer Engineering Co., Ltd. 1479 Kamimizu Honmachi, Kodaira City

Claims (1)

【特許請求の範囲】[Claims] 実装基板に形成さｉｔだ第１群のボンディング部から延
在する配線部を前記ボンディング部の幅より小さくし、
該配線部間に第２群のボンディング部を形成して成り、
前記第１群および第２群のボンディング部に半導体チッ
プに対するワイヤをボンディングして成ることを特徴と
する半導体装置、A wiring portion extending from the first group of bonding portions formed on the mounting board is made smaller than the width of the bonding portion;
A second group of bonding parts is formed between the wiring parts,
A semiconductor device, characterized in that wires for a semiconductor chip are bonded to the bonding portions of the first group and the second group,
JP57216921A 1982-12-13 1982-12-13 Semiconductor device Pending JPS59107551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57216921A JPS59107551A (en) 1982-12-13 1982-12-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57216921A JPS59107551A (en) 1982-12-13 1982-12-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59107551A true JPS59107551A (en) 1984-06-21

Family

ID=16696008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57216921A Pending JPS59107551A (en) 1982-12-13 1982-12-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59107551A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868638A (en) * 1986-11-15 1989-09-19 Matsushita Electric Works, Ltd. Plastic molded pin grid chip carrier package
JPH0334337A (en) * 1990-06-06 1991-02-14 Seiko Epson Corp semiconductor integrated circuit
EP0382445A3 (en) * 1989-02-10 1991-04-17 Honeywell Inc. High density bond pad design
JPH0348230U (en) * 1989-09-16 1991-05-08
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5359227A (en) * 1991-07-12 1994-10-25 Vlsi Technology, Inc. Lead frame assembly and method for wiring same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868638A (en) * 1986-11-15 1989-09-19 Matsushita Electric Works, Ltd. Plastic molded pin grid chip carrier package
EP0382445A3 (en) * 1989-02-10 1991-04-17 Honeywell Inc. High density bond pad design
JPH0348230U (en) * 1989-09-16 1991-05-08
JPH0334337A (en) * 1990-06-06 1991-02-14 Seiko Epson Corp semiconductor integrated circuit
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5359227A (en) * 1991-07-12 1994-10-25 Vlsi Technology, Inc. Lead frame assembly and method for wiring same

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