JPS63111720A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To eliminate a fault at output inversion by setting a prescribed relation to a delay amount of a couple of delay circuits of a CMOS inverter receiving a signal input directly and with a delay and connecting the output to a common buffer. CONSTITUTION:A P-channel transistor (TR) P1 and an N-channel TR N1 of the 1st CMOS inverter IV1 are connected in series between a power supply VDD and a ground VSS, a signal from an input signal node 10 is inputted to its gate and the output is given at an output node 13. Similarly, the 2nd CMOS inverter IV2 consists of a P-channel TR P2 and an N-channel TR N2, its output is connected to the output node 13 and delay circuit 11, 12 are connected to each pre-stage. The delay circuits 11, 12 consist respectively of N-channel TRs N3, N4 whose gate receives a potential VDD and P-channel TRs P3, P4 whose gate receives a potential VSS, and the size of the TR P3 is selected larger than that of the TR P4 and the size of the TR N4 is selected larger than that of the TR N3. Thus, overshoot/undershoot at output inversion and the through- current are suppressed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an output buffer circuit provided in a semiconductor integrated circuit, and particularly relates to an output buffer circuit in which two stages of CMOS inverters share a common output line. MOS (insulated gate type) connected like this
Regarding the output circuit.

(Prior art) Conventionally, as an LSI output parallel circuit, the circuit shown in Fig. 6 (,)
Alternatively, they are configured as shown in FIGS. 7 to 10, respectively. That is, the output buffer circuit of FIG. 6(,) is as follows.
The drains of a P-channel transistor P whose source is connected to the vDD power supply and an N-channel transistor N1 whose source is connected to the power supply (ground potential) are connected to the output line 61, and their gates are connected to each other. CMOS inverter IV connected tangentially to signal power M62
Consisting of In addition, each output 2177 in FIGS. 7 to 10
The circuit includes a first CMOS inverter vI to which the input signal is directly inputted and a second CMOS inverter vI to which the input signal is inputted through a delay circuit vo'' or 80 or 90 or 100m.
MOS inverters IV are connected to share an output line 61. In this case, the delay circuit 70 in FIG.
consists of one delay element DL, and the delay circuit 8 in FIG.
0 is composed of a plurality of delay elements DL... connected in series, and the delay circuit 90 in FIG. 9 is composed of a plurality of delay elements DL...
are connected in parallel to form the delay circuit 100 in FIG.
The gate is v8. The nep channel transistors P and r connected to ii and 7'? are connected to v0 potential and 7'? :,
CMO in which N-channel transistors N are connected in parallel
This is an S delay circuit.

However, the output buffer circuit shown in FIG.
When the output circuit is driven, voltage oscillations occur in the power supply lines 63, 64 and the output line 61 due to the resonant circuit consisting of a, Lb, Lc and the load capacity -iC of the output line 61, causing an undervoltage in the output signal shown in FIG. 6(b). A sheet and oversheating phenomenon occurs. As a result, the power supply voltage fluctuates, causing problems such as malfunctions and latch-up phenomena in other elements connected to the same power supply line as the output circuit.

9. Each of the output buffer circuits shown in FIGS. 7 to 10 drives the load in two stages using the first CMOS inverter IV and the second CMOS inverter Ivt, so there is no overshade or undershade. Although the shading phenomenon is somewhat suppressed, the P-channel transistor P, , the N-channel transistor N, of the second CMOS inverter IV,
Since a common delay circuit is connected to each ff-) of
When the output of the output circuit is inverted, the P-channel transistor P
, , N-channel transistors N are simultaneously on, and a through current flows between the vDDt source and the vB source. This through current causes the power supply voltage to fluctuate, which poses a problem of inducing malfunctions in other elements.

(Problems to be Solved by the Invention) As described above, the present invention solves the problems caused by power supply voltage fluctuations caused by overshading, undershading phenomena, and through currents occurring during output inversion. This was created to solve the problem of inducing malfunction of elements, and can suppress the open and undershoot phenomenon and through current when the output is reversed, and prevent malfunction of other elements that share the power supply. An object of the present invention is to provide an output buffer circuit that can prevent this.

[Objective of the Invention] (Means for Solving the Problems) The output buffer circuit of the present invention includes a first CMOS inverter to which a signal input is directly input, and a first CMOS inverter to which the signal input is inputted via a first delay circuit. ), and a second CMOS inverter consisting of a P-channel transistor input to the circuit and an N-channel transistor to which the signal input is input via a second delay circuit, and each output node of the two-stage inverter is connected in common. It is characterized by becoming.

(Function) By appropriately setting the delay amounts of the first delay circuit and the second delay circuit, overshading and undershading phenomena at the time of output inversion can be suppressed, and the rise time and fall time can be reduced. It becomes possible to set it freely, and moreover, it becomes possible to suppress the through current of the second CMOS inverter. Therefore, it is possible to prevent malfunction of other elements that share the power supply with the output buffer circuit.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a nine-output buffer circuit installed in an LSI.
IV, is the vDDIIIC source end and V. P channel MO8) is connected between the voltage source terminal (ground potential) and resistors P1 and N.
Channel MO8) is a first CMOS inverter in which transistors N8) are connected in series and each f-) is commonly connected and connected to the signal input node 10. IV, also has vDD1/ as the primitive end and v8. 'dL between the source end and the progenitor end
channel MO8) transistor P, and N channel MO
8) A second CMO in which transistors N are connected in series.
It is an S inverter. The signal input node 10 and the P-channel transistor P! of the second CMOS inverter IV1! A first delay circuit 11 and a second delay circuit 12 are connected between the gates of the N-channel transistors N, and the two (D CMOS inverters IV1, IV, +7) correspondingly. Each output node is commonly connected to a signal output node 13.

The above two delay circuits 11 and 12 correspond to CM
An O8 delay circuit is used, and the first delay circuit 11 includes a P-channel transistor P whose gate is given a v0 potential, and a P-channel transistor P whose gate is given a vDD potential 7'? ,N? The second delay circuit 12 has a Janel transistor N and is connected in parallel, and the second delay circuit 12 has a gate given the v0 potential and 7'tP.
A channel transistor P4 and an N-channel transistor N whose f-) is given a DD potential are connected in parallel.

The delay time of the first delay circuit 11 is the transistor P!
The delay time of the second delay circuit 12 depends on the on-resistance of the transistor P 4 e N4, and each delay time has a desired value having a predetermined magnitude relationship. Each transistor P above
A size of 8 t N3 * P 4 I N4 is set. In this example, the size of transistor P is set larger than the size of transistor P4, and the size of transistor N4 is set larger than the size of transistor N.

Next, the operation of the output buffer circuit will be explained.

Now, when the signal input node 10 is lowered from the vDD potential to the v0 potential, the first CMOS inverter IV1 has P
Channel transistor P8 is turned on, and the load is charged with a small driving force from transistor P1.
The signal output node 13 starts to rise from the vsB potential. At this time, in the second CMOS inverter IV,
First, the N-channel transistor N of the second delay circuit 12 on the N-channel r-to side.

is turned on, the N-channel transistor N
, turns off rapidly. Thereafter, the P-channel transistor P of the first delay circuit 11 on the P-channel foot side is turned on, thereby turning on the P-channel transistor P. At this time, the on-resistance of the P-channel transistor P of the first delay circuit 11 increases due to the back gate bias effect as the gate potential of the P-channel transistor P decreases, so that the gate potential decreases gradually. Become something. Further, the delay circuit 11ON channel transistor N of the i1 functions to finally bring the gate potential to a completely low level. As a result, the output potential of the output node 13 rises slowly, and the charging/discharging current (output current) at that time can be small. That is, the input/output characteristics of the output buffer circuit during the above operation, and the voltage changes at each point are shown, for example, in Figure 2 (solid lines in al), and the time changes in the output current are shown in Figure 2 (solid lines in bl). Here, for comparison, the transfer characteristics and output current characteristics of the conventional output buffer circuit shown in FIG. 6(a) are shown by dotted lines.

Contrary to the above, input node IQ is vs, +41st to v
When raising the potential to the DD potential, the N-channel transistor N1 of the first CMOS inverter IV is turned on, and the output node 13 is discharged by the small driving force of this transistor N1, and the output node 13 becomes vDD. ′
It starts to fall from around rJL. At this time, the second CMOS
In inverter IV, vc, first, P channel r-
first delay circuit 110P channel transistor P on the side
, turns on rapidly turning off the P-channel transistor P.

After this, the second delay circuit 12 on the N-channel gate side is turned on.
By turning on channel transistor N4,
N-channel transistor N is turned on. At this time,
the second delay circuit 12ON channel transistor N;
As the f-) potential of the N-channel transistor N increases, the ion resistance increases due to the back gate bias effect, so the rise in the r-) potential becomes gradual. Further, the P-channel transistor P of the second delay circuit I2 functions to finally bring the r-) potential to a completely high level. As a result, the output potential of the output node 13 rises slowly, and the charging/discharging current at that time can be small.

That is, according to the output 7177 circuit of the above embodiment, compared to the output buffer circuit of the conventional example, the output node and the power line opergate, which occurs in proportion to the charge/discharge current of the load.
undersea, -) phenomenon can be suppressed. Moreover, it is possible to prevent a through current between the vDDt sources, v, . . . when the output potential is inverted, and power consumption can be reduced.

Furthermore, since the final output current: ft is the sum of the respective output currents of the two-stage CMOS inverters, there is no loss due to the two-stage circuit division, and a large output current can be obtained.

Note that the present invention is not limited to the above embodiments,
a P-channel gate of a second CMOS inverter IV;
N channel? -) by inserting delay circuits with different delay amounts on the input side of the P-channel gate and the N-channel r
-) by controlling each gate voltage independently of each other, the output waveform rise time (Rlse time)
, various modifications can be made to suppress the fall time. That is, for example, the third
As in the output buffer circuit shown in the figure, the signal input node 1
0 and the second CMOS inverter IV, P-channel r-
), and an nfcp channel transistor p, whose gate is connected to the v0 potential, is inserted between the signal input node 10 and the N channel r-to of the second CMOS inverter IV, and r-) is at the vDD potential. An N-channel transistor N connected to the N-channel transistor N may be inserted. In addition, when applied to an output 7171 circuit in a semi-custom IC such as a gate array, a delay circuit in which a plurality of delay elements each having a unit delay time are connected in series or parallel as shown in Fig. 4 or Fig. 5 is used. By providing a circuit, the rise time and fall time of the output waveform can be easily set freely by selecting the number of elements.

In addition, in the output buffer circuit shown in FIG. 4 above, P, ・
... Fip channel ff-) P-channel transistors, N, . . . are delay elements connected in series on the input side, and N-channel transistors are delay elements connected in series on the N-channel gate input side. In addition, in the output buffer circuit shown in FIG. 5, P, . . . are P channel/L/
P-channel transistors, N, . . . which are delay elements connected in parallel with each other on the gate input side are N-channel transistors which are delay elements connected in parallel with each other on the N-channel gate input side.

In each of the output buffer circuits shown in FIGS. 3 to 5, the same parts as in FIG. 1 are given the same reference numerals.

[Effects of the Invention] As described above, the output buffer circuit of the present invention can suppress overshading, undershoot phenomena, and through current during output inversion, and prevent malfunctions of other elements sharing the power supply. can do.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an embodiment of the output buffer circuit of the present invention, and Figures 2 (,) and (b) show the transfer characteristics and output current characteristics of the circuit in Figure 1 compared to the characteristics of the conventional circuit. Figures 3 to 5 are circuit diagrams showing other embodiments, and Figures 6 (,) and 7 to 10 are circuit diagrams showing conventional output buffer circuits, respectively. Figure 6 (
b) is a waveform diagram showing an example of input/output voltages of the circuit of Fig. 1(a). DESCRIPTION OF SYMBOLS 10... Signal input node, 11... First delay circuit, 12... Second delay circuit, 13... Signal output node, IVl, IV, ・CMOS inverter, P, ~
P, −P channel transistor, N, ~N, . . . N channel transistor. Applicant's representative Patent attorney Takehiko Suzue Figure 1 (b) Figure 2 Figure 3 Figure 4 Figure 5

Claims (3)

[Claims] (1) It has a first CMOS inverter to which a signal input is directly input and a second CMOS inverter to which the signal input is input through a delay circuit, and each output node of these two stages of inverters is connected in common. In the output buffer circuit, the delay circuit includes a first delay circuit and a second delay circuit separately provided corresponding to the input side of the P-channel gate and the input side of the N-channel gate of the second CMOS inverter. An output buffer circuit characterized in that the delay amount of the first delay circuit and the delay amount of the second delay circuit are set to have a predetermined relationship. (2) The first delay circuit and the second delay circuit each include a P-channel transistor whose gate is given a low-level potential and a N-channel transistor whose gate is given a high-level potential.
CMOS in which channel transistors are connected in parallel
a delay circuit, the size of the P-channel transistor of the first delay circuit is larger than the size of the P-channel transistor of the second delay circuit, and the size of the N-channel transistor of the second delay circuit is larger than the size of the P-channel transistor of the second delay circuit; 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is larger than the size of an N-channel transistor. (3) The first delay circuit is composed of one P-channel transistor or a plurality of P-channel transistors connected in series or in parallel, each of which has a low-level potential applied to its gate, and
The delay circuit of 1 has a high-level potential applied to its gate.
2. The output buffer circuit according to claim 1, comprising a plurality of N-channel transistors connected in series or in parallel.