JPS60214630A - Complementary gate circuit - Google Patents

Abstract

PURPOSE:To reduce a penetration current by constituting the complementary gate circuit by connecting gates of an N and a PIGFET to drains of an N and a PIGFET whose sources are connected to an input terminal and then connecting the common drain of the former N and PIGFETs to an output terminal. CONSTITUTION:An input signal from a terminal 5 is applied to sources of N and PIGFETs Q3 and Q5, whose outputs are inputted to gates of N and PIGFETs Q4 and Q6 to obtain the output of the common drain at a terminal 8. The time when the FETs Q6 and Q4 are both on is the period from the ''L'' level to the ''H'' level of the input to the terminal 5 and a penetration current flows only in this period. This period is right before the FETQ4 turns on right before the FETQ6 turns off and the penetration current flowing from the FETQ6 to the FETQ4 is small. Further, almost no penetration current flows in the transition of the input signal from the ''H'' level to the ''L'' level because the FETQ6 begins to turn on and the FETQ4 begins to turn off nearly at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a complementary gate circuit using complementary insulated gate field effect transistors.

(Prior art) Figure 1 is a circuit diagram showing an example of a conventional complementary gate circuit.
FIGS. 2(a) and 2(b) are operational waveform diagrams.

N-channel insulated gate field effect transistor (hereinafter referred to as
It is called an N-channel IGFET. ) Ql and the drains of P-channel IGFETQ* are commonly connected to output 2, the gates are commonly connected to input 1, and P-channel IGFETQ
The source of 2 is connected to the high potential power supply Vcc, and the N-channel IGFE
The source of TQI is connected to low potential power supply V8g.

In this conventional example, as shown in FIG.
When transitioning to the "L level", there is a time when IGFETs Ql and Q2 are simultaneously turned on, so there is a time when IGFETs Ql and Q2 are turned on at the same time.
), the P-channel IGFETQ is connected to the power supply vCC.
Power supply Vl18 through z and N channel IGFETQl
Through current ID flows through.

Similarly, a NAND circuit with complementary III GFET configuration.

Through current also flows in NO-circuit circuits and the like. Complementary IG
In an LSI with a FET configuration, the gate circuits usually change simultaneously in synchronization with a certain clock, so a current equal to the sum of the through current flows, and since there is power supply wiring impedance from the LSI terminal to the internal elements of the LSI, the power supply There is a drawback that the voltage drop due to the through current in the Vcc and VSS power supply wirings is large.

In order to reduce this voltage drop, the power supplies vCC and v1
It would be better if the power supply wiring impedance of 18 was made smaller,
The width of the power supply lines for the power supplies Vcc and V8B must be increased, which has the drawback of increasing the chip area of the LSI. In addition, the voltage drop between Vcc and V[ll+ has the disadvantage of slowing down the switching time, and is one of the causes of circuit malfunction due to the ground level rising.

(Object of the Invention) An object of the present invention is to provide a gate circuit (including an inverter circuit) with a small through-current by eliminating the above-mentioned drawbacks.

(Structure of the Invention) The complementary gating circuit of the present invention has one input connected to the source of the first ON-channel insulated gate field effect transistor and the source of the first P-channel insulated gate field effect transistor, and the first The drain of the tenth N-channel insulated gate field effect transistor is connected to the gate of the second N-channel insulated gate field effect transistor, and the drain of the tenth P-channel insulated gate field effect transistor is connected to the second P-channel insulated gate field effect transistor. e the gate of the field effect transistor, the first ON channel insulated gate is connected to the gate of the field effect transistor;
connected to the power supply of the first P-channel insulated gate) U
One gate of the field effect transistor is connected to a second power supply, and the second ON channel insulated gate field effect transistor and the second P channel insulated gate field effect transistor are connected to form a complementary circuit. It consists of a circuit.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and represents the basic circuit of the complementary gate circuit of the present invention.

In this embodiment, one input 5 is the first ON channel GFET.
Source of Q3 and first P-channel IGFE T Q5
is connected to the source of IGFETQ3, and the drain of IGFETQ3 is connected to the second
is connected to the gate of N-channel IGFETQ4 of
The drain of FETQs is the second P-channel IGFETQ
The gate of IGFB T Q3 is connected to the high potential power supply Vcc as the first power supply, and the gate of IGFB T
The gate of FETQ5 is connected to the second 5- low potential power supply ■8B as a power supply, and the gate of IGFET
The drain of Q4 is connected to the drain of IGF'ETQII and output 8, and the source is connected to the power supply VssK, IGFETQ11
+7) and 7- are connected to the power supply Vcc, respectively.

Fig. 4 Ta) to ie) are the operating waveform diagrams of Fig. 3, including input 5 (+8 in the same figure)), connection point 6 (Fb in the same figure)),
The voltage waveform of connection point 7 ((C) in the same figure) and output 8 ((d) in the same figure) with respect to time and the waveform of the through current In (((d) in the same figure)
e)). The voltage at connection point 6 is the low level voltage of input 5 (vTP + ΔvTP)
It only goes down to E gusset. (Here, VTP is the threshold voltage of the P-channel IGFET, and ΔVTP is its change with respect to the back gate.) Furthermore, even if the high level of the input 5 reaches Vcc, the voltage at the connection point 7 is Vcc - (V It can only rise up to TEN+Δ■τN). (Here, VtN
Threshold voltage of 1jN channel IGFET, ΔVTN
is its change with respect to the back gate. ) Figure 4 [
As can be seen from bl and te), the time when IGFETs Q6 and Q4 are on simultaneously is the time tl when the input 5 is between "L level" 6-1 and "H level", and the through current is during the period tl. It just flows. Furthermore, during the period [l], just before IGFETQs is about to turn off, IGPET
Immediately after Q4 is turned on, IGFE'l'' is turned on from Q6.
The through current flowing through GPETQ< is several times smaller than that of a conventional inverter circuit. Also, when input 5 transitions from “H level” to “L level”, IG
Since PETQ6 starts to turn on and IGPETQ4 starts to turn off almost at the same time, almost no through current flows.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.
Represents an AND gate. Q71 Q81 Q9+QI
O is a P-channel IGFET, Qll, Ql2. Q
ts, Ql4 is N-channel IGFET, N-channel IGFETQII, Ql2 and P-channel IGF
ETQy and Qs constitute a basic circuit shown in FIG. Therefore, this embodiment can provide a NAND gate with a small through-current as in FIGS. 3 and 4.

Furthermore, by exchanging the power supplies Vll[l and Vcc in FIG. 5 and exchanging the P-channel type and the N-channel type, it is possible to provide an NO-operation circuit with less through-current than a two-man powered NO-operation gate.

(Effects of the Invention) As described above in detail, the complementary gate circuit of the present invention has the above structure, and the magnitude of the through current can be reduced to several times lower than that of the conventional gate circuit. have an effect.

Therefore, the voltage drop due to the power supply wiring impedance can be reduced to a few minutes, and the delay in switching time due to the voltage drop in the power supply and the rise in the ground level can be reduced, and the voltage drop due to the voltage drop and the rise in the ground level can be reduced. It is possible to prevent idle operation due to collisions, to reduce the width of the Ae wiring for power supply and ground to the gate circuit, and to provide an a-complementary 111GFET L8I with a correspondingly smaller chip size.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional complementary gate circuit.
FIG. 2 is a diagram of its operating waveforms, FIG. 3 is a circuit diagram showing one embodiment of the present invention, FIG. 4 is a diagram of its operating waveforms, and FIG. It is a circuit diagram showing an example of. 1...Input, 2...Output, Death...
・Input, 8... Output, A, B... Input, Vcc, Vss... Power supply, Ql. Qs, Q4+ Qlll Ql21 Ql31 Ql
4...N-channel insulated gate field effect transistor, Q21 Qs, Qs, Q? . Q8. Q9. Qlo...P-channel insulated gate field effect transistor. 9- Vss z l Figure V? Figure z3 Figure foil 5 Figure 7゜Name 4 Figure

Claims (1)

[Claims] one input is connected to the source of the first N-channel insulated gate field effect transistor and the source of the first P-channel insulated gate field effect transistor, and the drain of the first N-channel insulated gate field effect transistor is connected to the source of the first N-channel insulated gate field effect transistor; the drain of the first P-channel insulated gate field-effect transistor is connected to the gate of the second N-channel insulated gate field-effect transistor; The gate of the first N-channel insulated gate field effect transistor is connected to a first power supply, and the gate of the first N-channel insulated gate field effect transistor is
The gate of the channel insulated gate field effect transistor is connected to a second power supply, and the second N channel insulated gate field effect transistor and the second P channel insulated gate field effect transistor constitute a complementary circuit. A complementary gating circuit characterized in that the circuit comprises a circuit connected in such a manner that