JPS6297347A - One-chip microcomputer with gate array - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a connection portion of a signal input from a gate array section to a microcomputer section of a one-chip microcombinator with a gate array.

[Summary of the invention]

The present invention connects a cell having a pull-up means and a pull-down means to the input signal line from the gate array section to the micro combinator section of a one-chip combinatorial unit with a gate array, and uses a mask process to print wiring on the gate array section. , it is now possible to select either pull-up or pull-down of the signal, or connection with the signal of the gate array section, and it is now possible to easily perform pull-up or pull-down when the signal of the gate array section is not connected. It is something.

[Conventional technology]

In a conventional one-chip microcomputer with a gate array, as in Japanese Patent Application No. 59-167049, signals input from the gate array section to the microcomputer section are connected to the gate array by placing one end of the wiring aluminum around the GA section. It was intended to connect the necessary signals to the wiring in the section. FIG. 2 shows a layout diagram of a conventional semiconductor chip. In the figure, 1 is a semiconductor substrate, 2 is a RAM, 3 is a ROM, 4 is a CPU section, 5 is an input/output board, and 6 is an internal path, which constitute a microconverter section.

7 is a gate array section, 8 is an input/output section .mu., and 9 is an array of base V sections .mu.. At the boundary between the gate array section and the micro combinator section, one end of aluminum wiring for various signals is placed so that it can be connected to the gate array section. In the figure, reference numeral 10 is an interrupt signal, which is an input signal from the gate array section to the micro combinator section. In addition, the signal introduced into the gate array section is fixedly connected to the power supply voltage VDD or VB2.
A signal line is also required to provide the If the signal input from the gate array section to the micro combinator section is not used, this signal should be VDD or 111. of ■I. EEl.

It is necessary to prevent current from flowing into the gate circuit to which this signal is input, or if the micro combinator section operates unstable due to the signal being given.

For this reason, it was necessary to connect the signal giving the VDD or VSS through wiring in the gate array section.

[Problems and objects to be solved by the invention] However, in the above-mentioned prior art, the limited wiring area is limited to VDD or VSS.
I have to say that it is a waste of time because it is used only for the purpose of giving.

The present invention is intended to solve these problems, and its purpose is to make it possible to effectively utilize the wiring area. Yet another object is to provide an easy method of automation with CAD. [Means for Solving the Problems] The one-chip microcomputer with a gate array of the present invention is connected to the signal of the micro combinator section which allows input from the gate array section as needed, The signal line is placed at the boundary of the computer section, and the signal line is 1 μm thick in the mask process that burns the wiring on the gate array section.
It is characterized by having an interface cell that can be selected for up, pull down, or connection to a signal in the gate array section.

〔Example〕

FIG. 1 is a layout diagram of a semiconductor chip of a one-chip microcomputer with a gate array in an embodiment of the present invention. In the figure, 11 is an interferon.

Figure 3 shows the interface 7μ in the embodiment of Figure 1.
FIG. In this example, CMO8 structure 7μ
Uses mini-layer wiring. 12 in the figure is an interface cell. 16 and 18 are the second layer aluminum with currents VDD and VB11, respectively. Reference numeral 17 indicates the boundary of the sea urchin μ, with the upper side being the N-well region and the lower side being the P-well region. 14.15
15 is an N+ diffusion, and 15 is a diffusion for applying a potential to the N- sea urchin μ from the power source VDD, which is connected to the N0 diffusion from the second layer aluminum of the power source via the first layer aluminum. On the other hand, 14
is a diffusion that obtains a potential of VDD from N-y, and this is connected to the first layer of aluminum. 19.20 is P ten diffusion,
Similar to 14 and 15, 19 applies a potential to the P-well, and 20
13 is a signal line made of polysilicon and has a contact 21°22923 between the polysilicon and the first layer aluminum.Electric wire 16 The upper side is the micro converter section, 13 is its input signal, and the lower side of the power supply 18 is the gate array section. The signal input from the gate array to the micro combinator section is formed by connecting the contact 25 with the first layer of aluminum.If the signal from the gate array section is not required, the contact 2 is connected to the contact 25.
1 and the N+ diffusion 14 are connected with the first layer of aluminum and pulled up, or the contact 22 and the P+ diffusion 20 are connected with the first layer of aluminum and pulled down. In this cell, the microcomputer section is arranged at the boundary of the gate array section and connected to each of the signal lines input from the gate array section to the micro combinator section.

〔Effect of the invention〕

As described above, according to the present invention, signals that do not require input from the gate array section are pulled up or pulled down inside the interface cell, so there is no need for extra wiring in the gate array section. It disappears. or,
Since the interface cell of the present invention can utilize the area of the power supply aluminum, there is no increase in area by arranging the cells. Also, by using the same cell for many signals, the method of adding the first layer of aluminum for pull-up or pull-down can be generalized.

This can facilitate programming of the CAD system that actually performs this process.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor chip of a one-chip microcomputer with a gate array according to the present invention.011...interface cell FIG. 2 is a layout diagram of a semiconductor chip of a conventional one-chip microcomputer with a gate array. FIG. 5 is a pattern diagram of the interface cell in FIG. 1. 13...Polysilicon signal lines 14, 15-
...N10 diffusion 16...Power supply (VDD) aluminum 17...
・Sea urchin μ boundary 1B・・・Voltage #(Vss) Aluminum 19.20-・
...P10 Diffusion 21. 22.23...Polysilicon and #1
Aluminum contacts or better

Claims (1)

[Claims] In a one-chip microcomputer with a gate array that has a microcomputer section and a gate array section on the same semiconductor substrate and enables signal wiring between them, it is possible to input from the gate array section as necessary. It is connected to the signal of the microcomputer section and is placed at the boundary between the gate array section and the computer section, and the signal line is pulled up or down during the mask process of baking the wiring into the gate array section, or connected to the signal inside the gate and array section. A one-chip microcomputer with a gate array, which is characterized by having a selectable interface cell.