JPS6364054B2 - - Google Patents
Info
- Publication number
- JPS6364054B2 JPS6364054B2 JP57066823A JP6682382A JPS6364054B2 JP S6364054 B2 JPS6364054 B2 JP S6364054B2 JP 57066823 A JP57066823 A JP 57066823A JP 6682382 A JP6682382 A JP 6682382A JP S6364054 B2 JPS6364054 B2 JP S6364054B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- connection
- pins
- pads
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明はモノリシツク集積回路、特にチツプの
外部接続端子の接続を改良したところのモノリシ
ツク集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic integrated circuit, and more particularly to a monolithic integrated circuit in which the connection of external connection terminals of a chip is improved.
モノリシツク集積回路（以下ICという）は１
個の半導体のチツプ内に作られた集積回路であつ
て、最近における大規模集積回路の発展は目覚ま
しい。ICは回路素子が一つの例えばシリコンな
どの半導体のチツプ内に作り込まれ、チツプ上面
に設けられた外部接続端子（以下パツドという）
をパツケージの外部リード端子（以下ピンとい
う）と例えばアルミニウムなどのリード線で接続
することにより集積回路装置としてでき上る。 Monolithic integrated circuit (hereinafter referred to as IC) is 1
Large-scale integrated circuits are integrated circuits fabricated within individual semiconductor chips, and the recent development of large-scale integrated circuits has been remarkable. In an IC, circuit elements are built into a single semiconductor chip such as silicon, and external connection terminals (hereinafter referred to as pads) are provided on the top surface of the chip.
An integrated circuit device is completed by connecting the external lead terminals (hereinafter referred to as pins) of the package with lead wires made of aluminum or the like.
これまでICは必要とする回路機能毎にチツプ
を形成し、一方１４，１６ピンDIP（デユアルイ
ンラインパツケージ）のように標準化されている
パツケージに合せて、チツプのパツドとピンとの
接続パターンを定めていた。従つてこの接続パタ
ーンはほぼチツプ毎に定まりあまり問題となるこ
とはなかつた。しかしながら最近に至り、ゲート
アレイのようにマスタスライスを作成しこの一つ
のマスタスライスから数10〜数1000ゲートに及ぶ
数種の集積回路を作成することが行われるように
なつてきている。そしてそれらのチツプは入出力
数に応じてそれぞれ例えば５２，４４，４０，２
８ピンのように異なるピン数のパツケージに収納
される。この場合各チツプは一つのマスタスライ
スで形成されるためそのパツドは皆同一に配設さ
れているので、これをパツケージのピンに合せて
どう接続するかの、リード線の接続パターンを定
めなければならない。このためチツプのパツドの
接続が、種々のパツケージに合せて最も合理的に
行われるよう、接続の自由度が大であることが望
まれるに至つている。 Up until now, IC chips have been formed for each required circuit function, and the connection pattern between the pads and pins of the chip has been determined in accordance with standardized packages such as 14- and 16-pin DIPs (dual in-line packages). Ta. Therefore, this connection pattern was almost fixed for each chip and did not pose much of a problem. However, recently, it has become common practice to create a master slice like a gate array, and to create several types of integrated circuits ranging from several tens to several thousand gates from this single master slice. And those chips are respectively 52, 44, 40, 2 depending on the number of inputs and outputs.
They are housed in package cages with different numbers of pins, such as 8-pin. In this case, since each chip is formed from one master slice, its pads are all arranged in the same way, so it is necessary to determine the connection pattern of the lead wires to match the pins of the package and connect them. No. For this reason, it has become desirable to have a high degree of freedom in connection so that the pads of the chip can be connected most rationally in accordance with various packages.
第１図はかかる一従来例のICのチツプのパツ
ドとパツケージのピンとの接続を示すパターン図
である。ICのチツプ５０には１〜４４番の44個
のパツド５１がその周辺に配設されている。これ
に対しパツケージは１〜４０番の40個のピン５２
を有しており、それぞれリード線５３によりこれ
らのパツド５１とピン５２は接続されている。こ
の図でも分るように、パツド５１の１と２番、１
２と１３番、２３と２４番および３４と３５番と
はそれぞれお互に短絡状態に固定的に配線されて
おり、それぞれパツケージのピン５２の１，１
１，２１，３１番に２点接続の形で接続されてい
る。これらの２点接続は、通常リード線５３の抵
抗による電位変動を少くするために、電源端子
（Vcc、GND端子など）などに用いられる。これ
はチツプのパツド５１の面積は非常に小さいため
にリード線５３を２本一緒に接続することができ
ないためである。 FIG. 1 is a pattern diagram showing the connections between the pads of the chip and the pins of the package of such a conventional IC. Forty-four pads 51 numbered 1 to 44 are arranged around the IC chip 50. On the other hand, the package has 40 pins 52 numbered 1 to 40.
These pads 51 and pins 52 are connected by lead wires 53, respectively. As you can see in this diagram, pad numbers 1 and 2, 1
Nos. 2 and 13, Nos. 23 and 24, and No. 34 and 35 are fixedly wired in a short-circuited state, respectively, and are connected to pins 1 and 1 of pin 52 of the package, respectively.
It is connected to numbers 1, 21, and 31 in a two-point connection. These two-point connections are normally used for power supply terminals (V cc , GND terminals, etc.) in order to reduce potential fluctuations caused by the resistance of the lead wire 53 . This is because the area of the pad 51 of the chip is so small that two lead wires 53 cannot be connected together.
ところで、第１図に示したパターンによると、
１，２番のパツドから１番のピンに対する２点接
続を、都合により４０番のピンに変えようとして
も、２番のパツドからは先に接続された１番から
のリード線が邪魔して接続することができない。
すなわちこのパターンでは、２点接続点が固定さ
れてしまい種々のパツケージに対応して合理的に
接続パターンを設定できないという欠点を有して
いる。 By the way, according to the pattern shown in Figure 1,
Even if I tried to change the two-point connection from pads 1 and 2 to pin 1 to pin 40 for some reason, the lead wire from pad 2, which was connected earlier, would get in the way. Unable to connect.
That is, this pattern has the disadvantage that the two-point connection points are fixed, and connection patterns cannot be set rationally to accommodate various packages.
本発明の目的は、上記の欠点を除去することに
より、チツプのパツドとパツケージのピンとの接
続の自由度を増し、ピン数の異なる複数のパツケ
ージに対してもそれぞれ合理的な接続パターンを
得ることのできるチツプからなるモノリシツク集
積回路を提供することにある。 The purpose of the present invention is to increase the degree of freedom in connecting the pads of a chip and the pins of a package by eliminating the above-mentioned drawbacks, and to obtain rational connection patterns for multiple packages with different numbers of pins. The object of the present invention is to provide a monolithic integrated circuit consisting of a chip that can perform the following steps.
本発明のICは、チツプの角部を挟んで相隣る
二つの辺に設けられたパツドの中、少くとも一つ
の前記角部を挟んで相隣接する２個以上の前記パ
ツドが短絡されてなることからなつている。 In the IC of the present invention, two or more of the pads provided on two sides adjacent to each other with a corner of the chip sandwiched therebetween are short-circuited. It comes from becoming.
以下、本発明について図面を参照して詳細に説
明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第２図は、本発明の第１の実施例のICの第１
図と同様にチツプ５０のパツド５１とパツケージ
のピン５２とのリード線５３による接続を示すパ
ターン図である。この実施例は本発明を第１図に
示した従来例のICに適用したもので、参照数字
も同じものについては同一にしてある。なお簡略
化のためパツド５１とピン５２の番号は一部省略
してある。 FIG. 2 shows the first IC of the first embodiment of the present invention.
It is a pattern diagram showing a connection between a pad 51 of a chip 50 and a pin 52 of a package by a lead wire 53, similar to the figure. In this embodiment, the present invention is applied to the conventional IC shown in FIG. 1, and the same reference numerals are the same. Note that some numbers of pads 51 and pins 52 are omitted for simplicity.
この実施例が第１図の従来例と異なる点は、２
点接続用として相互に短絡してあるパツド５１
が、この実施例では４４と１番、１１と１２番、
２２と２３番、および３３と３４番と、チツプ５
０の角部を挟んで相隣る二つの辺に設けられたパ
ツド５１の中、前記角部を挟んで相隣接した２個
の端子がそれぞれ短絡されていることである。そ
してピンへの接続は第１図に示したと同じくなる
ようそれぞれ１，１１，２１番および３１番のピ
ンに対して行われている。 This embodiment differs from the conventional example shown in FIG. 1 in two points.
Pads 51 shorted together for point connection
However, in this example, 44 and 1, 11 and 12,
22 and 23, and 33 and 34, and chip 5
Among pads 51 provided on two sides adjacent to each other with a corner of the pad 51 in between, two terminals that are adjacent to each other with the corner in between are short-circuited. Connections to pins are made to pins 1, 11, 21, and 31, respectively, in the same manner as shown in FIG.
第３図は、本発明の第２の実施例のICのこれ
までと同様な接続のパターン図である。この実施
例は第２図に示した第１の実施例において、２点
接続される相手のピンの番号を、１→４０番、１
１→１０番、２１→２０番および３１→３０番へ
変えたものである。既に説明したように第１図に
示した従来例では、２点接続される相手のピン番
号は固定されていたけれども、本発明の実施例に
よると、従来のように先に接続されたリード線の
邪魔が無くなるので、チツプの角を挟むいずれの
側のピンにも接続することができる。 FIG. 3 is a diagram showing the same connection pattern as before for the IC according to the second embodiment of the present invention. This embodiment differs from the first embodiment shown in FIG.
The numbers were changed from 1 to 10, 21 to 20, and 31 to 30. As already explained, in the conventional example shown in FIG. 1, the pin numbers of the two-point connections are fixed; Since there are no obstacles in the way, you can connect to pins on either side of the chip.
第４図は、本発明の第３の実施例のICのこれ
までと同様な接続のパターン図である。この実施
例では、２点接続用として短絡してあるパツド５
１は、これまでの実施例とは異なり角部を挟んで
は１と４４番および１１と１２番にとどめ、他方
は従来のやり方により２１と２２番および３２と
３３番に選んである。この実施例においては、パ
ツド１，１１の接続の自由度を持たものである。
すなわちパツト１をピン１，４０のいずれにも、
パツド１１をピン１０，１１のいずれにも接続す
ることが可能になつている。 FIG. 4 is a diagram showing the same connection pattern as before for an IC according to a third embodiment of the present invention. In this embodiment, pad 5 is shorted for two-point connection.
1 is limited to numbers 1 and 44 and numbers 11 and 12 on both sides of the corner, unlike the previous embodiments, and numbers 21 and 22 and numbers 32 and 33 are selected in the conventional manner. In this embodiment, the pads 1 and 11 have a degree of freedom in connection.
In other words, if part 1 is connected to either pin 1 or 40,
It is now possible to connect pad 11 to either pin 10 or 11.
第５図は、本発明の第４の実施例のICのこれ
までと同様な接続のパターン図である。この実施
例は本発明を３点接続がある場合に適用したもの
である。すなわち４４，１，２番、１０，１１，
１２，１３番、２２，２３，２４番および３２，
３３，３４，３５番のパツド５１がそれぞれ、短
絡されて、１，１１，２１および３１番のピン５
２にリード線５３を用いて接続されている。この
実施例においても前述の２点接続の場合と同様に
接続の自由度が増し合理的な接続パターンが得ら
れることは明らかである。 FIG. 5 is a diagram showing the same connection pattern as before for an IC according to a fourth embodiment of the present invention. In this embodiment, the present invention is applied to a case where there is a three-point connection. That is, 44, 1, 2, 10, 11,
No. 12, 13, 22, 23, 24 and 32,
Pads 51 No. 33, 34, and 35 are shorted to pins 51 No. 1, 11, 21, and 31, respectively.
2 using a lead wire 53. It is clear that in this embodiment as well, the degree of freedom in connection is increased and a rational connection pattern can be obtained, as in the case of the two-point connection described above.
以上の説明は、ICのチツプとしてパツドが44
個、パツケージとしてピン数が40個のものについ
て行なつたけれども、本発明はこれらの実施例に
限定されることなく、一般に任意の複数のパツド
を有するICに適用されることは言うまでもない。 The above explanation is based on the fact that the pad is used as an IC chip.
Although the present invention has been described for a package having 40 pins, it goes without saying that the present invention is not limited to these embodiments, but is generally applicable to ICs having any number of pads.
以上詳細に説明したとおり、本発明のモノリシ
ツク集積回路は、チツプの少くとも一つの角部を
挟んで相隣接して２個以上の短絡された外部接続
端子を有しているので、チツプの外部接続端子と
パツケージの外部リード端子との接続の自由度が
増し、外部リード端子の異るパツケージに対して
もそれぞれ合理的な接続パターンを得ることでき
ると言う効果を有している。 As explained in detail above, the monolithic integrated circuit of the present invention has two or more short-circuited external connection terminals adjacent to each other with at least one corner of the chip in between. This has the effect that the degree of freedom in connection between the connection terminal and the external lead terminal of the package is increased, and that rational connection patterns can be obtained for packages with different external lead terminals.
第１図は従来例の、第２〜第５図はそれぞれ本
発明の第１〜第４の実施例の、ICのチツプの外
部接続端子とパツケージのピンとの接続を示すパ
ターン図である。図において、５０……チツプ、
５１……外部接続端子（パツド）、５２……外部
リード端子（ピン）、５３……リード線、１〜４
４……パツドおよびピンの番号。
FIG. 1 is a pattern diagram of a conventional example, and FIGS. 2 to 5 are pattern diagrams showing connections between external connection terminals of an IC chip and pins of a package, respectively, of first to fourth embodiments of the present invention. In the figure, 50...chips,
51... External connection terminal (pad), 52... External lead terminal (pin), 53... Lead wire, 1 to 4
4...Pad and pin numbers.
Claims (1)
られた外部接続端子の中、少くとも一つの前記角
部を挟んで相隣接する２個以上の前記外部接続端
子が短絡されてなることを特徴とするモノリシツ
ク集積回路。1 Among the external connection terminals provided on two sides adjacent to each other with a corner of the chip in between, two or more of the external connection terminals that are adjacent to each other with at least one corner in between are short-circuited. A monolithic integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57066823A JPS58182841A (en) | 1982-04-21 | 1982-04-21 | Monolithic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57066823A JPS58182841A (en) | 1982-04-21 | 1982-04-21 | Monolithic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58182841A JPS58182841A (en) | 1983-10-25 |
| JPS6364054B2 true JPS6364054B2 (en) | 1988-12-09 |
Family
ID=13326943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57066823A Granted JPS58182841A (en) | 1982-04-21 | 1982-04-21 | Monolithic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182841A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6098645A (en) * | 1983-11-02 | 1985-06-01 | Mitsubishi Electric Corp | Manufacture of ic package |
-
1982
- 1982-04-21 JP JP57066823A patent/JPS58182841A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58182841A (en) | 1983-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6674177B2 (en) | Apparatus for implementing selected functionality on an integrated circuit device | |
| US4942317A (en) | Master slice type semiconductor integrated circuit having 2 or more I/O cells per connection pad | |
| JP2560805B2 (en) | Semiconductor device | |
| JPS6364054B2 (en) | ||
| JPH07118507B2 (en) | Semiconductor integrated circuit using bump mounting | |
| JPH02244755A (en) | LSI | |
| JP2594541B2 (en) | Semiconductor integrated circuit | |
| JPS59197151A (en) | Semiconductor integrated circuit device | |
| JPS61208237A (en) | Master slice integrated circuit | |
| JPS61225845A (en) | semiconductor equipment | |
| JP2900555B2 (en) | Semiconductor integrated circuit | |
| JPS6135546A (en) | semiconductor equipment | |
| JPH0221145B2 (en) | ||
| JPH04361538A (en) | large scale integrated circuit | |
| JPH0529546A (en) | Semiconductor integrated circuit | |
| JPH02306650A (en) | semiconductor equipment | |
| JPH023259A (en) | Manufacture of master slice type semiconductor device | |
| JPS63273332A (en) | Method for manufacturing semiconductor integrated circuit device | |
| JPS59145542A (en) | Large-scale integrated circuit | |
| JPS6278848A (en) | Large scale semiconductor integrated circuit | |
| JPH0815198B2 (en) | Large-scale integrated circuit device | |
| JPS59124151A (en) | Semiconductor integrated circuit device | |
| JPS63299135A (en) | Semiconductor integrated circuit device | |
| JPH0194637A (en) | Semiconductor integrated circuit | |
| JPH04184936A (en) | Semiconductor integrated circuit |