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JPS6081852A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6081852A
JPS6081852A JP58190218A JP19021883A JPS6081852A JP S6081852 A JPS6081852 A JP S6081852A JP 58190218 A JP58190218 A JP 58190218A JP 19021883 A JP19021883 A JP 19021883A JP S6081852 A JPS6081852 A JP S6081852A
Authority
JP
Japan
Prior art keywords
circuit
semiconductor substrate
circuit elements
elements
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58190218A
Other languages
Japanese (ja)
Inventor
Akira Yamagishi
明 山岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP58190218A priority Critical patent/JPS6081852A/en
Publication of JPS6081852A publication Critical patent/JPS6081852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/225—Correcting or repairing of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the size of a semiconductor substrate by forming auxiliary bonding pads for circuit elements and/or circuit networks separated from each other, and connecting fine metal wirings between the pads, thereby omitting the circuits with aluminum wirings. CONSTITUTION:A plurality of circuit elements 2, 3, 4, 5 which include bipolar transistors are formed on a semiconductor substrate 1, and electrically connected via the prescribed circuit network. Auxiliary bonding pads 6, 7 are formed to be disposed at the periphery on the elements 2, 3, and connected via fine metal wirings 8 such as gold wirings. Thus, it is not necessary to form aluminum wiring circuits along the periphery of the substrate 1, thereby reducing the size of the substrate 1.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特にバイポーラアナログ集
積回路装置において、相互に離隔する回路要素及び／又
は回路網間の電気的な接続構造の簡略化に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and in particular to the simplification of an electrical connection structure between mutually separated circuit elements and/or circuit networks in a bipolar analog integrated circuit device. be.

〔背景技術〕[Background technology]

１　一般にこの種集積回路装置は例えば第１図に示すよ
うに、半導体基板Ａに複数の回路要素Ｂ，Ｏ。1 Generally, this type of integrated circuit device includes a plurality of circuit elements B and O on a semiconductor substrate A, as shown in FIG.

Ｄ，Ｂを形成し、それぞれを所定の回路網にて電気的に
接続すると共に、半導体基板Ａの周辺に外部リード部材
との接続用のポンディングパッド部を形成して構成され
ている。D and B are formed and electrically connected to each other through a predetermined circuit network, and a bonding pad portion for connection with an external lead member is formed around the semiconductor substrate A.

ところで、この集積回路装置において、回路要素Ｂ及び
Ｃは比較的近い位置に形成されているにも拘わらず、そ
れぞれの間には種々の回路要素。By the way, in this integrated circuit device, although circuit elements B and C are formed relatively close to each other, there are various circuit elements between them.

回路網が複雑に形成されていることもあって、アノレミ
配線による回路にてストレートに接続することができな
い。従って、半導体基板Ａの周辺に沿って回路Ｆを形成
して回路要素Ｂ，Ｏの電気的な接続が行われている。Because the circuit network is complex, it is not possible to connect it straight using an anoremi wiring circuit. Therefore, a circuit F is formed along the periphery of the semiconductor substrate A to electrically connect the circuit elements B and O.

しかし乍ら、このような回路Ｆは他の回路要素。However, such a circuit F is another circuit element.

回路網を避けて形成する必要があることから、半導体基
板Ａは必然的に大形化しコストアリプするという問題が
ある。Since it is necessary to form the semiconductor substrate A while avoiding the circuit network, there is a problem that the semiconductor substrate A inevitably becomes larger and the cost increases.

〔発明の開示〕[Disclosure of the invention]

それ故に、本発明の目的は相互に離隔する回路要素及び
／又は回路網間の電気的な接続を、半導体基板を大形化
することなく、簡単かつ容易に行うことのできる半導体
装置を提供することにある。Therefore, an object of the present invention is to provide a semiconductor device in which electrical connections between mutually separated circuit elements and/or circuit networks can be easily and easily made without increasing the size of the semiconductor substrate. There is a particular thing.

そして、本発明の特徴は同一半導体基板に複数の回路要
素を形成し、それぞれを所定の回路網にて電気的に接続
したものにおいて、上記回路要素及び／又は回路網のう
ち、離隔する少くとも２つに補助のポンディングパッド
部を形成し、このポンディングパッド部間を金属細線に
て接続したことにある。A feature of the present invention is that a plurality of circuit elements are formed on the same semiconductor substrate and are electrically connected to each other through a predetermined circuit network, and at least one of the circuit elements and/or the circuit network is separated from the other. Auxiliary bonding pads are formed in the two, and the bonding pads are connected with a thin metal wire.

この発明によれば、相互に離隔する回路要素及び／又は
回路網に補助のポンディングパッド部が形成すれ、この
ポンディングパ・ソド部間が金属細線にて最短距離で接
続されている関係で、アルミ配線による回路の形成ヌベ
ーヌを完全に省略できる。このために、半導体基板を小
形化できる上、−コストも低減できる。According to this invention, auxiliary bonding pads are formed on circuit elements and/or circuit networks that are separated from each other, and the bonding pads and pads are connected by a thin metal wire at the shortest distance. The process of forming a circuit using wiring can be completely omitted. Therefore, not only can the semiconductor substrate be made smaller, but also the cost can be reduced.

〔発明を実施するための最良の形態３ 次に本発明のバイポーフアナログ集積回路装置への適用
例について第２図を参照して説明する。[Best Mode 3 for Carrying Out the Invention] Next, an example of application of the present invention to a bipolar analog integrated circuit device will be described with reference to FIG.

図において、１は半導体基板であって、それにはバイポ
ーラトランジスタを含む複数の回路要素２．３，４．５
が形成されており、所定の回路網にて電気的に接続され
ている。特に、回路要素２゜３には補助のポンデイング
パ・・ノド部６，７が周辺部に位置するように形成され
ており、全線などの金属細線８にて接続されている。In the figure, 1 is a semiconductor substrate, which includes a plurality of circuit elements 2.3, 4.5 including bipolar transistors.
are formed and electrically connected through a predetermined circuit network. In particular, auxiliary ponding pads 6, 7 are formed at the periphery of the circuit element 2.3, and are connected to each other by a thin metal wire 8 such as a full wire.

この実施例によれば、回路要素２，３のポンディングパ
リド部６，７間を金属細線８にて接続することにより、
従来のように半導体基板１の周辺に沿ってアルミ配線に
よる回路を形成する必要がなくなる。このために、半導
体基板ｌのサイズを小形化できる上、コストも低減でき
る。According to this embodiment, by connecting the bonding pad portions 6 and 7 of the circuit elements 2 and 3 with the thin metal wire 8,
There is no need to form a circuit using aluminum wiring along the periphery of the semiconductor substrate 1 as in the conventional case. Therefore, the size of the semiconductor substrate 1 can be reduced, and the cost can also be reduced.

尚、本発明において、補助のボンディングパノド部は回
路網に形成することもできる。Incidentally, in the present invention, the auxiliary bonding panod portion can also be formed in a circuit network.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は従来例及び本発明の一実施例を示す
平面図である。 図中、１は半導体基板、２〜５は回路要素、６゜７は補
助のボンディングパ・ソド部、８は金属細線である。 　５− 第１図 第２図 ７５1 and 2 are plan views showing a conventional example and an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 to 5 are circuit elements, 6° and 7 are auxiliary bonding pads, and 8 is a thin metal wire. 5- Figure 1 Figure 2 75

Claims (1)

【特許請求の範囲】[Claims] 同一半導体基板に複数の回路要素を形成し、それぞれを
所定の回路網にて電気的に接続したものにおいて、上記
回路要素及び／又は回路網のうち、離隔する少くとも２
つに補助のボンディングパ，ノド部を形成し、このボン
ディングパ・ソド部間を金属細線にて接続したことを特
徴とする半導体装置。In a device in which a plurality of circuit elements are formed on the same semiconductor substrate and electrically connected to each other through a predetermined circuit network, at least two of the circuit elements and/or circuit networks are separated from each other.
A semiconductor device characterized in that an auxiliary bonding pad and a groove are formed in the semiconductor device, and a thin metal wire is used to connect the bonding pad and the groove.
JP58190218A 1983-10-11 1983-10-11 Semiconductor device Pending JPS6081852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58190218A JPS6081852A (en) 1983-10-11 1983-10-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58190218A JPS6081852A (en) 1983-10-11 1983-10-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6081852A true JPS6081852A (en) 1985-05-09

Family

ID=16254434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58190218A Pending JPS6081852A (en) 1983-10-11 1983-10-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6081852A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6311669A (en) * 1986-06-30 1988-01-19 Ulvac Corp Cvd method
JPS6311668A (en) * 1986-06-30 1988-01-19 Ulvac Corp Cvd method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339891A (en) * 1976-09-24 1978-04-12 Nec Corp Semiconductor integrated circuit device
JPS54104286A (en) * 1978-02-02 1979-08-16 Matsushita Electric Ind Co Ltd Integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339891A (en) * 1976-09-24 1978-04-12 Nec Corp Semiconductor integrated circuit device
JPS54104286A (en) * 1978-02-02 1979-08-16 Matsushita Electric Ind Co Ltd Integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6311669A (en) * 1986-06-30 1988-01-19 Ulvac Corp Cvd method
JPS6311668A (en) * 1986-06-30 1988-01-19 Ulvac Corp Cvd method

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