JPS629661A - Monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the chip area of a monolithic integrated circuit for microwaves, by forming an inductor having a capacitor in series. CONSTITUTION:On a substrate 13 of dielectric such as sapphire or semi- insulating compound such as GaAs, a helical first conductive layer 12 is formed. Next, a second conductive layer 11 is formed through an insulating layer 14 of silicon oxide or silicon nitride on the conductive layer 12. The conductive layer 12 and the conductive layer 11 are separated from each other in direct current. At both ends of the conductive layer 11 an input terminal 11IN and an output terminal 11OUT are provided, and at both ends of the conductive layer 12 an input terminal 12IN and an output terminal 12OUT are provided. In this way, the inductance per unit conductor length of the inductor formed with the conductive layer 11 and the conductive layer 12 can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to monolithic integrated circuits, and in particular to monolithic integrated circuits for microwave applications. [Prior Art]
- Traditionally, this type of monolithic integrated circuit has two FETs 31.32 and 31.32, as shown in FIG.
Each load resistance 33.34, feedback resistance 35 of FET 31, and two DC cut capacitors 36.37
and an inductor 38 for peaking.

In conventional monolithic integrated circuits, it is usually
6.37 is composed of a parallel flat plate made of silicon oxide or silicon nitride as an insulator. Also, the inductor 38 is formed in a spiral shape to obtain a large inductance. In order to operate at low frequencies, it is necessary to increase the capacitance value of the capacitors 36 and 37, and a large area is required to form them.

Furthermore, the area occupied by the inductor 38 becomes very difficult, which is usually the case for monolithic integrated circuits.

Most of the tap area is occupied by capacitors and inductors.

[Problem that the invention seeks to solve]

The above-mentioned conventional monolithic integrated circuit has the disadvantage of being expensive due to its large chip area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost monolithic integrated circuit. a second conductive layer, an insulating layer disposed above the first conductive layer, a spiral second conductive layer provided on top of the first conductive layer via the insulating layer; 1
The second conductive layer includes an input terminal and an output terminal provided at both ends of the conductive layer and an input terminal and an output terminal provided at both ends of the second conductive layer.

A monolithic integrated circuit according to a second aspect of the present invention includes a spiral conductive layer @1 provided on a substrate, an insulator layer provided on the conductive layer J@1, and a spiral second conductive layer provided above the first conductive layer; an input terminal and an output terminal provided at both ends of the first conductive layer;
◎ [Embodiment] The first embodiment of the present invention will be described with reference to the drawings. 〇Figure 1 is a plan view showing an embodiment of the first invention of the present invention,
FIG. 2 is a sectional view taken along line AA' of the embodiment shown in FIG.

As shown in FIGS. 1 and 2, on a substrate 13 made of a dielectric material such as sapphire or a semi-insulating compound such as GaAs,
A spiral first conductive layer 12 is formed, and then a @2 conductive layer 11 is formed on the conductive layer 12 via an insulating layer 14 of silicon oxide or silicon nitride.

The conductive layer 12 and the conductive layer 11 are separated in terms of direct current,
An input terminal 11, N and an output terminal 110U'r are provided at both ends of the conductive layer 11, and an input terminal 12□ and an output terminal 120UT are provided at both ends of the conductive layer 12, respectively.
will be provided.

By configuring in this way, the conductive layer 11 and the conductive layer 1
It is well known that the inductance per unit length of the conductor of an inductor formed with 2 and 2 can be large. Since this inductor is used, it is possible to form this inductor within a normal process without adding a special process to form the circuit element of the present invention.

3 is an equivalent circuit diagram of the embodiment shown in FIG. 1. As shown in FIG. 3, the inductance 21 per unit length of the conductive layer 11 and the inductance 22 per unit length of the conductive layer 120 , and a capacitance 23 of the unit thickness between the IE layer 11 and the conductive layer 12, a composite circuit is constructed in which the inductance in series and the capacitance in series are M. Therefore, 4 of this composite circuit By setting the total inductance and total capacitance to the required values, customization equivalent to the conventional circuit described above can be obtained.

FIG. 4 is a circuit diagram showing an embodiment of the second aspect of the present invention.

In FIG. 4, numeral 39 indicates the above-mentioned composite circuit, and since there is no need to provide a capacitor for DC power, the chip area can be reduced.

This is a composite circuit of a capacitor and an inductor.

Not only can it be conveniently used in the crotch circuit of a two-stage amplifier as in the present embodiment, but it can also be used in the input circuit as part of a matching circuit to also serve as a DC cut for the input signal.

[Effects of the Invention] As explained above, the monolithic integrated circuit of the present invention has the following effects:
Monoriff for microwaves by forming an inductor with a capacitor in series.

Since the area of the integrated circuit can be reduced, the cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the first invention of the present invention;
Figure 2 is a sectional view taken along line A-A' of the embodiment shown in Figure 1;
The figure is an equivalent circuit diagram of the embodiment shown in Fig. 1, Fig. 4 is a circuit diagram showing an embodiment of the invention of g2 of the invention, and Fig. 5 is a circuit diagram showing an example of a conventional monoriff integrated circuit. It is. 11.12... Conductive layer, 13... Substrate, 14... Insulator layer, 21.22...
Inductance, 23... Capacitance, 3
1.32...FET, 33°34...
Load resistance, 35... Hot water speed resistance, 36.37...
...Capacitor. Figure 1 Kaya JI! I

Claims (2)

[Claims] (1) A spiral first conductive layer provided on a substrate;
an insulating layer provided on the conductive layer, a spiral second conductive layer provided on top of the first conductive layer via the insulating layer, and an input provided at both ends of the first conductive layer. A monolithic integrated circuit comprising a terminal, an output terminal, and an input terminal and an output terminal provided at both ends of the second conductive layer. (2) a spiral first conductive layer provided on the substrate;
an insulating layer provided on the conductive layer, a spiral second conductive layer provided on top of the first conductive layer via the insulating layer, and an input provided at both ends of the first conductive layer. A monolithic integrated circuit comprising: a terminal and an output terminal; an input terminal and an output terminal provided at both ends of the second conductive layer; and at least one transistor.