JPH0569311B2 - - Google Patents
Info
- Publication number
- JPH0569311B2 JPH0569311B2 JP14862385A JP14862385A JPH0569311B2 JP H0569311 B2 JPH0569311 B2 JP H0569311B2 JP 14862385 A JP14862385 A JP 14862385A JP 14862385 A JP14862385 A JP 14862385A JP H0569311 B2 JPH0569311 B2 JP H0569311B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- monolithic integrated
- circuit
- integrated circuit
- inductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000012212 insulator Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 description 8
- 239000002131 composite material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- -1 GaAs Chemical class 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はモノリシツク集積回路に関し、特にマ
イクロ波用のモノリシツク集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to monolithic integrated circuits, and more particularly to monolithic integrated circuits for microwave applications.
従来、この種のモノリシツク集積回路は、第５
図に示すように、２個のFET３１，３２と、
FET３１，３２それぞれの負荷抵抗３３，３４
と、FET３１の帰還抵抗３５と、２個の直流カ
ツト用のキヤパシタ３６，３７と、ピーキング用
のインダクタ３８とを備える。
Traditionally, this type of monolithic integrated circuit
As shown in the figure, two FETs 31 and 32,
Load resistances 33 and 34 for FETs 31 and 32, respectively
, a feedback resistor 35 of the FET 31, two DC cut capacitors 36 and 37, and a peaking inductor 38.
従来のモノリシツク集積回路では、通常キヤパ
シタ３６，３７は酸化シリコン又は窒化シリコン
を絶縁体とした平行平板キヤパシタにより構成さ
れる。また、インダクタ３８は大きなインダクタ
ンスを得るための螺旋状に形成される。 In conventional monolithic integrated circuits, capacitors 36 and 37 are usually constructed of parallel plate capacitors using silicon oxide or silicon nitride as an insulator. Further, the inductor 38 is formed in a spiral shape to obtain a large inductance.
このようなモノリシツク集積回路を低周波まで
動作させるためには、キヤパシタ３６，３７の容
量値を大きくする必要があり、これらの形成に大
面積を要する。 In order to operate such a monolithic integrated circuit up to low frequencies, it is necessary to increase the capacitance values of the capacitors 36 and 37, and a large area is required to form them.
さらに、インダクタ３８の占める面積も大きく
なり、通常この種のモノリシツク集積回路のチツ
プ面積の大部分はキヤパシタとインダクタとで占
められる。 Furthermore, the area occupied by the inductor 38 is also large, with the capacitor and inductor typically occupying most of the chip area of this type of monolithic integrated circuit.
上述した従来のモノリシツク集積回路は、チツ
プ面積が大きくなるので、高価になるという欠点
がある。
The conventional monolithic integrated circuit described above has the disadvantage of being expensive due to its large chip area.
本発明の目的は、低価格のモノリシツク集積回
路を提供することにある。 It is an object of the present invention to provide a low cost monolithic integrated circuit.
本発明のモノリシツク集積回路装置は、基板上
に設ける螺旋状の第１の導電層と、前記第１の導
電層の上に設ける絶縁体層と、前記絶縁体層を介
して前記第１の導電層の上部に設ける螺旋状の第
２の導電層と、前記第１の導電層の両端に設ける
入力端子および出力端子と、前記第２の導電層の
両端に設ける入力端子および出力端子とを含むこ
とを特徴とする。
The monolithic integrated circuit device of the present invention includes: a spiral first conductive layer provided on a substrate; an insulating layer provided on the first conductive layer; A spiral second conductive layer provided on the top of the layer, an input terminal and an output terminal provided at both ends of the first conductive layer, and an input terminal and an output terminal provided at both ends of the second conductive layer. It is characterized by
次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の一実施例を示す平面
図、第２図は第１図に示す実施例のＡ−A′線断
面図である。 FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line A-A' of the embodiment shown in FIG.
第１図および第２図に示すように、サフアイア
等の誘電体またはGaAs等の半絶縁性化合物の基
板１３上に、螺旋状の第１の導電層１２を形成
し、次に酸化シリコン又は窒化シリコンの絶縁体
層１４を介して導電層１２上に第２の導電層１１
を形成する。 As shown in FIGS. 1 and 2, a spiral first conductive layer 12 is formed on a substrate 13 of a dielectric material such as sapphire or a semi-insulating compound such as GaAs, and then a first conductive layer 12 of silicon oxide or nitride is formed. A second conductive layer 11 is formed on the conductive layer 12 via a silicon insulating layer 14.
form.
導電層１２と導電層１１とは直流的に分離され
ていて、導電層１１の両端にはそれぞれ入力端子
１１INおよび出力端子１１OUTが設けられ、導電層
１２の両端にはそれぞれ入力端子１２INおよび出
力端子１２OUTが設けられる。 The conductive layer 12 and the conductive layer 11 are separated in terms of direct current, and an input terminal 11 IN and an output terminal 11 OUT are provided at both ends of the conductive layer 11, respectively, and an input terminal 12 IN is provided at both ends of the conductive layer 12, respectively. and an output terminal 12 OUT are provided.
このように構成することにより、導電層１１と
導電層１２とで形成されるインダクタの導体の単
位長さ当りのインダクタンスが大きくとれること
は良く知られている。 It is well known that with this configuration, the inductance per unit length of the conductor of the inductor formed by the conductive layer 11 and the conductive layer 12 can be increased.
なお、FET等の素子を形成する場合には、２
層以上の導電層が用いられるため、本発明の回路
素子を形成するために特別に工程を増加すること
なく、通常の工程内でこのインダクタを形成する
ことが可能である。 In addition, when forming elements such as FET, 2
Since more than one conductive layer is used, it is possible to form this inductor within a normal process without adding a special process to form the circuit element of the present invention.
第３図は第１図に示す実施例の等価回路であ
る。 FIG. 3 is an equivalent circuit of the embodiment shown in FIG.
第３図に示すように、導電層１１の単位長さ当
りのインダクタンス２１、導電層１２の単位長さ
当りのインダクタンス２２、および導電層１１と
導電層１２との層間の単位長さ当りのキヤパシタ
ンス２３により、直列のインダクタンスと直列の
キヤパシタンスとを有する複合回路が構成され
る。 As shown in FIG. 3, the inductance 21 per unit length of the conductive layer 11, the inductance 22 per unit length of the conductive layer 12, and the capacitance per unit length between the conductive layer 11 and the conductive layer 12. 23 constitutes a composite circuit having a series inductance and a series capacitance.
従つて、この複合回路の総合インダクタンスお
よび総合キヤパシタンスを所要の値に設定するこ
とにより、前述した従来の回路と同等の特性が得
られる。 Therefore, by setting the total inductance and total capacitance of this composite circuit to required values, characteristics equivalent to those of the conventional circuit described above can be obtained.
第４図は本発明の第２の一実施例を示す回路図
である。 FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
第４図において、３９は上記した複合回路を示
し、直流カツト用のキヤパシタを設ける必要がな
いので、チツプ面積を小さくできる。 In FIG. 4, numeral 39 indicates the above-mentioned composite circuit, and since there is no need to provide a capacitor for DC cut, the chip area can be reduced.
このキヤパシタとインダクタとの複合回路は、
本実施例の如く２段増幅器の段間回路に使用され
るばかりでなく、入力回路に用いて整合回路の１
部として用い、入力信号の直流カツトを兼ねるこ
とも可能である。 This composite circuit of capacitor and inductor is
In addition to being used for the interstage circuit of a two-stage amplifier as in this embodiment, it can also be used for the input circuit and one of the matching circuits.
It can also be used as a direct current cutter for input signals.
以上説明したように本発明のモノリシツク集積
回路は、直列にキヤパシタを有するインダクタを
形成することにより、マイクロ波用のモノリシツ
ク集積回路のチツプ面積を小さくできるので、価
格を低減できるという効果がある。
As explained above, the monolithic integrated circuit of the present invention has the effect of reducing the cost because the chip area of the monolithic integrated circuit for microwaves can be reduced by forming an inductor having a capacitor in series.
第１図は本発明の第１の一実施例を示す平面
図、第２図は第１図に示す実施例のＡ−A′線断
面図、第３図は第１図に示す実施例の等価回路
図、第４図は本発明の第２の一実施例を示す回路
図、第５図は従来のモノリシツク集積回路の一例
を示す回路図である。
１１，１２……導電層、１３……基板、１４…
…絶縁体層、２１，２２……インダクタンス、２
３……キヤパシタンス、３１，３２……FET、
３３，３４……負荷抵抗、３５……帰還抵抗、３
６，３７……キヤパシタ。
1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' of the embodiment shown in FIG. 1, and FIG. 3 is a plan view of the embodiment shown in FIG. 1. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a circuit diagram showing an example of a conventional monolithic integrated circuit. 11, 12... conductive layer, 13... substrate, 14...
...Insulator layer, 21, 22...Inductance, 2
3... Capacitance, 31, 32... FET,
33, 34...Load resistance, 35...Feedback resistance, 3
6,37...capacity.
Claims (1)
記第１の導電層の上に設ける絶縁体層と、前記絶
縁体層を介して前記第１の導電層の上部に設ける
螺旋状の第２の導電層と、前記第１の導電層の両
端に設ける入力端子および出力端子と、前記第２
の導電層の両端に設ける入力端子および出力端子
とを含むことを特徴とするモノリシツク集積回路
装置。1 A spiral first conductive layer provided on a substrate, an insulator layer provided on the first conductive layer, and a spiral conductive layer provided on the first conductive layer via the insulator layer. a second conductive layer; an input terminal and an output terminal provided at both ends of the first conductive layer;
1. A monolithic integrated circuit device comprising an input terminal and an output terminal provided at both ends of a conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14862385A JPS629661A (en) | 1985-07-05 | 1985-07-05 | Monolithic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14862385A JPS629661A (en) | 1985-07-05 | 1985-07-05 | Monolithic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS629661A JPS629661A (en) | 1987-01-17 |
| JPH0569311B2 true JPH0569311B2 (en) | 1993-09-30 |
Family
ID=15456924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14862385A Granted JPS629661A (en) | 1985-07-05 | 1985-07-05 | Monolithic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS629661A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677407A (en) * | 1992-04-06 | 1994-03-18 | Nippon Precision Circuits Kk | Semiconductor device |
| TW275152B (en) * | 1993-11-01 | 1996-05-01 | Ikeda Takeshi |
-
1985
- 1985-07-05 JP JP14862385A patent/JPS629661A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS629661A (en) | 1987-01-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |