JPS6260835B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for forming a Josephson device pattern by a low-temperature lift-off method, and particularly relates to the formation of an upper electrode pattern.

[Background of the invention]

Switching devices using Josephson junctions have performance superior to Si semiconductor devices by about two orders of magnitude in terms of switching time and power consumption, and are considered promising as high-speed logic and memory devices. The electrodes and interlayer insulating film of this Josephson device are patterned by a lift-off method.
The manufacturing process is carried out at a low temperature of 70°C or less to prevent deterioration of device characteristics. The lift-off mask is a so-called resist stencil mask in which a positive type photoresist 12 is coated on a substrate 11 and developed with C ₆ H ₅ Cl after exposure, as shown in Fig. 1, so that the cross-sectional structure of the resist is overhanging. It is being The most important manufacturing process in a Josephson device is the base electrode and top electrode that form the Josephson junction. In particular, the resist mask used when forming the upper electrode is subject to spatter damage caused by oxygen ions. That is, under the influence of the high frequency sputtering cleaning of the base electrode bonding surface and the high frequency sputter oxidation treatment in an oxygen-containing atmosphere that forms a tunnel barrier, the overhang portion 23 of the resist is damaged as shown in FIG. On the other hand, Pb-In alloy is not used for the upper electrode material because it causes deterioration in device characteristics. For this purpose, Pb-Bi or Pb-Au-Pb alloy must be used. The biggest drawback of these electrode materials is that they are eroded by alkaline developers and water, so it is necessary to coat their surfaces with SiO as a protective film.

However, as shown in FIG. 3, the resist mask does not completely cover the sides of the Pb-Bi electrode pattern 33.
It is difficult to coat with SiO coat 34. Fourth
The figure shows Pb-Bi upper electrode pattern 4 after lift-off.
3 shows the coating state of the SiO coat film 44 of No. 3. This phenomenon caused serious problems as erosion progressed from the sidewalls of the pattern in the next photoresist process, causing frequent swelling and peeling of the upper electrode pattern as shown in FIGS. 5a and 5b.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a pattern of a Josephson device, which makes it possible to completely prevent swelling and peeling of the upper electrode pattern of a Josephson device.

[Summary of the invention]

In order to achieve the above object, the present invention provides the sixth
After depositing the upper electrode material Pb-Bi 63 as shown in Figure a, the sides of the resist mask 62 are lightly etched with a plasma assher using oxygen gas to a thickness of approximately 0.3 to 1.0 μm as shown in Figure 6b. After forming a gap, a SiO coat film was deposited. In addition,
Reference numeral 65 indicates a portion where the side surface of the resist is etched by a plasma assher. As a result, it became possible to completely cover the side surfaces of the upper electrode Pb--Bi pattern with the SiO coating film 64, as shown in FIG. 6c. Figure 6d shows the Pb after lift-off treatment and subsequent alkaline developer and water washing treatment.
- This shows the Bi electrode pattern. As a result, the erosion of the Pb-Bi electrode pattern, which had been a problem in the past, was completely prevented, and there was no blistering or peeling. FIG. 7 shows the relationship between the plasma assher time and the etching amount (in the lateral direction) for resist using plasma assher using oxygen gas. Etching conditions are resist thickness
1.5μm, pressure 0.5Torr, output 50W.

Examples will be described in detail below.

[Embodiments of the invention]

Example 1 A cross-sectional view of a Pb-based Josephson logic element formed according to the present invention is shown in FIG.

The substrate has a diameter of 50 mmφ and a thickness of 350 μm <100>.
A Si substrate 81 is used. Note that on the Si substrate 81
A 600nm thermal oxide film is applied. This Si substrate 8
1, a Nb film with a thickness of 300nm was applied using a high-speed sputtering method.
was applied to form a ground plane 82.

After that, Nb ₂ O ₅ was added to the Nb surface by anodizing.
83 was formed to a thickness of 150 nm, and then SiO 84 was deposited to a thickness of 200 nm as an interlayer insulating film. A resist mask for the base electrode was formed on this under the following conditions. AZ1350J (AZ Company product) is formed to a thickness of 0.8 μm and prebaked in air at 70°C for 30 minutes. Then, after exposing the desired pattern, it was immersed in a C ₆ H ₅ Cl solution for 10 minutes, and further developed for 90 seconds using an alkaline developer. The composition of the developer is
AZ Teperotspur (trade name of AZ Company): Water = 1:1 was used. The Si substrate 81 was inserted into a vacuum chamber under the above conditions, and spatter cleaning was performed with Ar to remove moisture and dirt adsorbed on the surface of the SiO 84.

The conditions at this time were 480V and Ar pressure of 3×10 ^-3 Torr.
Sputtering time is 5 minutes. Next, after reducing the degree of vacuum in the vacuum chamber to 5×10 ⁻⁷ Torr, layered deposition of Au, Pb, and In was performed in this order using a resistance heater. The film thicknesses are 4nm, 160nm, and 36nm. After vapor deposition, in order to form a surface protective film, oxygen gas is introduced into the vacuum chamber to 1 atm, and then the temperature of the vacuum chamber is lowered.
Oxidation treatment was performed at 60°C for 60 minutes. After this,
The substrate 81 was taken out from the vacuum chamber and lifted off in acetone to form a base electrode 85. Next, a resist mask for the bonding window hole 87 is formed in the same manner as for the base electrode, and after performing spatter cleaning with Ar in the vacuum chamber again,
SiO was deposited to a thickness of 270 nm. Lift-off was performed in the same manner as for the base electrode described above to form a bonding window hole 87. Next, a resist mask for the upper electrode was produced under the following conditions. AZ1350J resist was formed to a thickness of 1.5 μm and heated in air at 70℃ for 30 minutes.
I did a pre-bake for a few minutes. Then, after exposing the desired pattern, it was immersed in a C ₆ H ₅ Cl solution for 10 minutes, and then
Development was performed for 90 seconds using an alkaline developer. The composition of the developer is the same as that of the base electrode. However, the exposure time was set to twice that of the conditions described above. After reducing the pressure in the vacuum chamber again, the base electrode surface was spatter cleaned with oxygen gas. Conditions are the same as for the base electrode. However, the gas species is the aforementioned oxygen.
Subsequently, oxygen gas was introduced to form a tunnel barrier, and after the pressure was set to 8×10 ^-3 Torr, the voltage was set at 360V.
A tunnel barrier 86 was formed by high frequency sputter oxidation treatment for 20 minutes. Next, after reducing the vacuum in the vacuum chamber to 5 × 10 ^-7 Torr, Pb-Bi (29wt%) was deposited to a thickness of 420 nm by simultaneous vapor deposition using a resistance heater, and then taken out from the vacuum chamber and subjected to plasma ashing. It was inserted into the vacuum chamber of the device. once 5x
After reducing the pressure to 10 ^-2 Torr, oxygen gas was introduced and the inside of the vacuum chamber was set at 0.5 Torr, and plasma ashing treatment was performed at an output of 50 W for 1 minute. At this time, the amount of etching in the lateral direction of the resist was approximately 0.7 μm. After this, successively insert it into a vacuum chamber,
Once the vacuum level was set to 5 x 10 ^-6 Torr, oxygen gas was introduced and the vacuum was set at 3 x 10 ^-3 Torr, spatter cleaning was performed at 480V for 3 minutes, and then the vacuum level was set at 5 x 10 -3 Torr.
Depressurize the vacuum chamber to 10 ^-6 Torr and reduce the film thickness as a protective film.
100 nm of SiO was deposited. After vapor deposition, it was taken out from the vacuum chamber and lifted off in acetone to form an upper electrode 88 and a protective film SiO 89. Next, a substrate 81 was inserted as an interlayer insulating film using the same resist mask as the upper electrode. For spatter cleaning, use Ar gas 3x
Process for 3 minutes at 10 ^-6 Torr and 480V output.
After reducing the pressure to 6×10 ⁻⁶ Torr, SiO was deposited to a thickness of 600 nm. It was taken out from the vacuum chamber again and lifted off in acetone to form an interlayer insulating film 90. Next, apply a resist mask for the control line to the above-mentioned upper electrode,
It was fabricated using the same method as the interlayer insulating film. It was inserted into the vacuum chamber again, and after spatter cleaning with Ar, layered deposition of Pb, Au, and In was performed in this order at 5×10 ⁻⁷ Torr or less. The film thickness is 540nm, respectively.
10nm, 250nm. After adhering, take it out from the vacuum chamber and perform lift-off in acetone to remove the control wire 9.
1 was formed. Finally, apply SiO as a protective film with a thickness of 1.3
It was formed by depositing .mu.m and lift-off. As mentioned above, in the fabrication of the upper electrode, Pb-Bi
After deposition, a plasma assher treatment using oxygen gas is performed, and then a protective film of SiO is applied.A new process was adopted to complete the fabrication of a Pb-based Josephson logic element.

〔Effect of the invention〕

As described above, the Josephson logic element manufactured according to the present invention can completely prevent erosion from the edges of the Pb--Bi electrode pattern, which has been a problem in the past, and there is no swelling or peeling. As a result, the superconducting properties were not degraded, the manufacturing process was extremely stable, and the yield was significantly improved. Furthermore, it was confirmed from the superconducting properties that there was no effect of oxidation on Pb-Bi due to oxygen plasma assher.

In the present invention, it has also been confirmed that even when Pb--Au--Pb is used as the upper electrode material, good superconducting properties can be obtained similar to Pb--Bi.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the resist mask, Figure 2 is a cross-sectional view of the missing overhang, Figure 3 is a cross-sectional view showing poor coverage of the SiO coating film, and Figure 4 is a cross-sectional view of the Pb-Bi electrode pattern after lift-off. 5a and 5b are cross-sectional views showing swelling and peeling of the upper electrode pattern, FIG. 6 a is a cross-sectional view after Pb-Bi deposition, and FIG. 6 b is a cross-sectional view after plasma assembling according to the present invention. Figure 6c is a cross-sectional view of the Pb-Bi electrode pattern completely covered with the SiO coating film, and Figure 6d is the Pb-Bi electrode pattern after lift-off.
FIG. 7 is a cross-sectional view of an electrode pattern, FIG. 7 is a diagram showing the relationship between plasma ashing time and etching amount, and FIG. 8 is a cross-sectional view of a Pb-based Josephson logic element formed according to the present invention. Explanation of symbols 11, 21, 31, 41, 51,
61, 81...Substrate, 12, 22, 32, 62...
...Resist mask, 23... Resist overhang lost due to spatter, 33, 43, 5
3,63,...Pb-Bi upper electrode, 34,44,
54, 64... SiO coat film, 65... Side surface of resist etched by plasma assher, 81... Si substrate, 82... Nb ground plane, 83... Nb ₂ O ₃ anodic oxide film, 84... Interlayer insulating film, 85... Base electrode, 86... Tunnel barrier, 87... Junction window hole, 88... Upper electrode, 89... SiO coat film, 90... Interlayer insulating film, 91... Control line, 92 ……Protective film.

Claims (1)

[Claims] 1. A method for forming a Josephson device pattern, which includes the following steps. (1) A step of applying a positive photoresist onto a substrate, (2) A step of irradiating a desired portion of the photoresist with ultraviolet light and then performing a development process to form a photoresist pattern, (3) A step of applying the photoresist to a lift-off mask. (4) After depositing the superconducting film, a gap is created between the superconducting film on the substrate and the photoresist by etching the exposed part of the photoresist by performing plasma asshiring using oxygen gas. (5) After the plasma assembling described above, a step of depositing a SiO film of 100 to 150 nm around the superconducting film on the substrate; (6) After depositing the SiO film, the step of performing a lift-off treatment. A method for forming a pattern of a Josephson element, characterized by the following. 2. The method for forming a pattern of a Josephson element according to claim 1, wherein the oxygen plasma assher is performed at an oxygen gas pressure of 0.3 to 0.6 Torr and an output of 10 to 100 W for 1 to 2 minutes. 3 Pb-Bi, Pb-Bi-Au, Pb- as superconducting films
3. A method for forming a pattern of a Josephson element according to claim 1 or 2, characterized in that any one of Au--Pb alloys is used.