JPS6167975A - Manufacture of josephson junction element - Google Patents
Manufacture of josephson junction elementInfo
- Publication number
- JPS6167975A JPS6167975A JP59188917A JP18891784A JPS6167975A JP S6167975 A JPS6167975 A JP S6167975A JP 59188917 A JP59188917 A JP 59188917A JP 18891784 A JP18891784 A JP 18891784A JP S6167975 A JPS6167975 A JP S6167975A
- Authority
- JP
- Japan
- Prior art keywords
- tunnel barrier
- electrode
- barrier layer
- superconductor electrode
- superconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000992 sputter etching Methods 0.000 claims abstract description 9
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 229910000978 Pb alloy Inorganic materials 0.000 claims abstract description 5
- 239000002887 superconductor Substances 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 238000011109 contamination Methods 0.000 abstract description 3
- 229910052745 lead Inorganic materials 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- KRTSDMXIXPKRQR-AATRIKPKSA-N monocrotophos Chemical compound CNC(=O)\C=C(/C)OP(=O)(OC)OC KRTSDMXIXPKRQR-AATRIKPKSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はジョセフソン接合素子の製造方法に関し、さら
に詳しくは高品質で微細な接合が得られるジョセフソン
接合素子の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a Josephson junction element, and more particularly to a method for manufacturing a Josephson junction element that allows high quality and fine junctions to be obtained.
（従来技術の問題点）
ジョセフソン接合素子で構成される論理回路や記憶回路
には、接合特性が優れ、この特性の各部（Ｎｂ）または
Ｎｂ化合物を、第２の超伝導体電極に鉛（ｐｂ）またＩ
ｆｉＰｂ合金を用いたものが注目されている。しかしな
がら、従来Ｐｂ系材料の適切なパターニング技術がなか
っ念几めに、Ｎｂ系／酸化物ＺＰｂ系接合のトンネル障
壁部を規定する技術はりフトオフ法に限られていた。(Problems with the prior art) Logic circuits and memory circuits composed of Josephson junction elements have excellent junction characteristics, and parts of these characteristics (Nb) or Nb compounds are applied to the second superconductor electrode using lead (Nb) or Nb compounds. pb) Also I
Those using fiPb alloy are attracting attention. However, in the absence of an appropriate patterning technique for Pb-based materials, the technique for carefully defining the tunnel barrier portion of the Nb-based/oxide ZPb-based junction has been limited to the lift-off method.
従来例どして、アール・エフ・プルーム（Ｒ，Ｆ。A conventional example is R.F. Plume (R,F.
Ｂｒｏｏｍ）等によって１９８０年１０月に発表された
アイ・イーｅイーーイー参トランズアクションズ・オン
・エレクトロン・デバイシーズ（ＩＥＢＥ ’１ｒａｎ
ｓａｅｔｉｏｎｓｏｎ ＥＩｅｃｔｒｏｒ＋ Ｄｅｖｉ
ｃｅｓ）の第ＲＤ−２７巻第１０号１９９８〜２００８
頁の論文などがある。この方法を第３図（、）〜（ｄ）
を用いて工程順に説明する。第３図（ａｌに示すように
、絶縁体基板あるいは表面に絶縁体層を有する基板３１
上に、蒸着法やスパッタ法によりＮｂから々る第１の超
伝導体電極３２を形成する。第１の超伝導体電極のパタ
ーニングは通常のホトレジスト工程を用いたエツチング
法やリフトオフ法で行なう。次に第３図（ｂｌに示すよ
うに第１の超伝導体電極３２上のトンネル障壁部となる
部分にアンダーカット形状のレジストマスク３３を形成
し、第３図（ｃｌに示すように基板表面に蒸着、法で一
酸化ケイ素（８ｉｏ）から々る絶縁体層３４を被着し、
引き続きリフトオフすると第３図（ｄｌに示すような開
口部をもつトンネル障壁部が形成される。この方法では
、トンネル障壁部がこの形成過程で直接大気にさらされ
ｆ：、す、レジスト処理を受けること（（より汚染され
る。しかも、トンネル障壁を形成する際にはこの汚染Ｍ
を除去するためにスパッタクリーニングが必要であるが
、トンネル障壁部はこの処理によってイオンダメージを
受けたり、絶縁体層３４からのスパッタ物により汚染さ
れたりする。アンダーカット形状のレジストマスク３３
け通常のホトレジスト工程に加え、露光前にクロロベン
ゼンなどの有機溶剤に浸すことによって得られるが、マ
スク形状はレジストのプリベーク条件や有機溶剤の液温
、ディップ時間などの影響を受けやすい。特に、トンネ
ル障壁部の有効面積を規定するレジストマスク３３下部
の寸法を精度よく得ることは非常に難しい。IEBE '1ran Transactions on Electron Devices (IEBE '1ran) announced in October 1980 by
saetionson EIector+ Devi
ces) Volume RD-27 No. 10 1998-2008
There are pages of papers, etc. This method is shown in Figures 3(,) to (d).
The process will be explained in order using . As shown in FIG. 3 (al), an insulating substrate or a substrate 31 having an insulating layer on the surface
A first superconductor electrode 32 made of Nb is formed thereon by vapor deposition or sputtering. Patterning of the first superconductor electrode is carried out by an etching method using a normal photoresist process or a lift-off method. Next, as shown in FIG. 3 (bl), an undercut-shaped resist mask 33 is formed on the portion of the first superconductor electrode 32 that will become the tunnel barrier section, and as shown in FIG. An insulating layer 34 made of silicon monoxide (8io) is deposited by a vapor deposition method,
Subsequent lift-off forms a tunnel barrier with an opening as shown in FIG. ((more polluted.Moreover, when forming the tunnel barrier, this pollution M
Although sputter cleaning is necessary to remove the insulator layer 34, the tunnel barrier section may be damaged by ions or contaminated by sputtered substances from the insulator layer 34. Undercut-shaped resist mask 33
In addition to the usual photoresist process, the mask shape can be obtained by soaking it in an organic solvent such as chlorobenzene before exposure, but the shape of the mask is easily affected by the resist prebaking conditions, the temperature of the organic solvent, and the dipping time. In particular, it is very difficult to accurately obtain the dimensions of the lower part of the resist mask 33 that defines the effective area of the tunnel barrier section.
（発明の目的）
本発明は、このような従来の欠点を取り除いたジョセフ
ソン接合素子の製造方法を提供することにある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a Josephson junction device that eliminates such conventional drawbacks.
（発明の構成）
本発明によれば、基板上ＫＮｂま念はＮｂ化合物からな
る第１の超伝導体電極とこの第１の超伝導に電極の一表
面上のトンネル障壁層、およびこのトンネル障壁Ｍを介
して前記第１の超伝導体電極層対向するＰｂまたＶｉＰ
ｂ合金からなる第２の超伝導体電極を有するジョセフソ
ン接合素子の製造方法において、基板上に第１の超伝導
体電極、この第１の超伝導体電極上にトンネル障壁層、
このトンネル障壁上に第２の超伝導体電極を連続形成す
る工程、前記第２の超伝導体電極上のトンネル障壁部と
なる場所にエツチングマスクを形成し、Ａｒと０．との
混合ガスを用いたイオンエツチング法により前記第２の
超伝導体電極の前記エツチングマスク以外の箇所を完全
にエツチングしてトンネル障壁部を規定する工程を含む
ことを特徴とするジョセフソン接合素子の製造方法が得
られる。(Structure of the Invention) According to the present invention, the KNb layer on the substrate includes a first superconductor electrode made of an Nb compound, a tunnel barrier layer on one surface of the electrode on the first superconductor, and a tunnel barrier layer on one surface of the electrode. Pb or ViP facing the first superconductor electrode layer through M
A method for manufacturing a Josephson junction device having a second superconductor electrode made of a b alloy, a first superconductor electrode on a substrate, a tunnel barrier layer on the first superconductor electrode,
In the step of continuously forming a second superconductor electrode on the tunnel barrier, an etching mask is formed on the second superconductor electrode at a location that will become the tunnel barrier portion, and Ar and 0.05% are etched. A Josephson junction element comprising the step of completely etching a portion of the second superconductor electrode other than the etching mask by an ion etching method using a mixed gas with a gas mixture to define a tunnel barrier portion. A manufacturing method is obtained.
（構成の詳細な砦、明）
以下本発明の基本プロセスについて図面を用いて説明す
る。(Details of the structure, clear) The basic process of the present invention will be described below with reference to the drawings.
第１図（ａｌに示すように、絶縁体基板あるいは表面に
絶縁体層を有する基板１１上に、ＮｂまたはＮｂ化合物
からなる第１の超伝導体電極１２、トンネル障壁層１３
、ＰｂまたけＰｂ合金から々る第２の超伝導体電極１４
０３層膜を形成する。第１の超伝導体重ｒｉ１２および
第２の超伝導体電極１４は蒸着法やスパッタ法で被着す
る。トンネル障壁層１３け第１の超伝導体電極１２表面
を熱酸化やプシズマ酸化するか、絶縁体膜などを被着し
て形成する。上記３層膜１２，１３．１４のバターニン
グは通常のホトレジスト工程を用いたエツチング法やリ
フトオフ法で行彦う。次に、第１図（ｂ）に示すように
第２の超伝導体電極１４上のトンネル障壁部となる場所
にレジストマスク１５を形成した後、Ａｒ、！：０２の
混合ガスを用いたイオンエツチング法で第２の超伝導体
電極１４のエツチングマスク１５以外の箇所を完全にエ
ツチング除去し、第１図（Ｃ）に示すようなトンネル障
壁部を形成する。ここで、エツチングガスにＡｒと０．
の混合ガスを用いるのは、ＰｂのＮｂ、 ８：Ｏｔに対
する大きなエッチング選択比を得るためである。すなわ
ち、第２の超伝導体電極１４（Ｐｂ）のオーバーエツチ
ングで下地の第１の超伝導体電極１２（Ｎｂ）がトンネ
ル障壁層１３、第２の超伝導体電極１４に再付着して生
じる第１．第２の超伝導体電極１３．１４間のショート
を防ぎ、基板１１上の絶縁体層の膜厚を保持する念めで
ある。第２図にイオンエツチングにおけるエツチング速
度と０□分圧の関係を示す。０２分圧の増加に伴ない、
ＮｂとＳｔｏｗのエツチング速度が減少し、Ｐｂのエツ
チング速度はほとんど変化し添加することによりさらに
大＠に改善される。Ｏｌの添加効果Ｆｉ５ Ｘ １０−
’ Ｔｏｒｒ以上の０２分圧で特に顕著となる。一方、
０２分圧が増加するとレジスト（ＡＺ１３５０Ｊ）のエ
ツチング速度比は減少するが、この値は適切な０７分圧
以下であれば高精度のバター／転写を行々うのに充分で
あろう第２図は超伝導体材料としてＮｂ 、 Ｐｂを用
いた場合の結果であるが、それぞれＮｂ化合物、Ｐｂ合
金でも同様々結果が得られる。また、この方法では再現
性の良い矩形、のレジストマスクが利用できること、異
方性の強いエツチングができることから、高寸法精度の
微細加工が可能である。さらに、第１の超伝導体電極１
２、トンネル障壁層１３、第２の超伝導体１４の３層膜
を連続形成した後忙トンネル障壁部を規定するため、第
３図に示した従来法で問題となる大気中露出、レジスト
処理、スパッタクリーニングに依る汚染がない。As shown in FIG. 1 (al), a first superconductor electrode 12 made of Nb or a Nb compound and a tunnel barrier layer 13 are formed on an insulating substrate or a substrate 11 having an insulating layer on the surface.
, a second superconductor electrode 14 made of a Pb-straddling Pb alloy.
03 layer film is formed. The first superconductor weight ri12 and the second superconductor electrode 14 are deposited by vapor deposition or sputtering. The tunnel barrier layer 13 is formed by subjecting the surface of the first superconductor electrode 12 to thermal oxidation or pussism oxidation, or by covering it with an insulating film or the like. The three-layer films 12, 13, and 14 are patterned by an etching method or a lift-off method using a normal photoresist process. Next, as shown in FIG. 1(b), a resist mask 15 is formed on the second superconductor electrode 14 at a location that will become a tunnel barrier portion, and then Ar,! : The portions of the second superconductor electrode 14 other than the etching mask 15 are completely etched away by an ion etching method using a mixed gas of 02 to form a tunnel barrier portion as shown in FIG. 1(C). . Here, the etching gas contains Ar and 0.
The reason for using the mixed gas is to obtain a large etching selectivity of Pb to Nb and 8:Ot. That is, the over-etching of the second superconductor electrode 14 (Pb) causes the underlying first superconductor electrode 12 (Nb) to re-adhere to the tunnel barrier layer 13 and the second superconductor electrode 14. 1st. This is to prevent short circuits between the second superconductor electrodes 13 and 14 and to maintain the thickness of the insulator layer on the substrate 11. FIG. 2 shows the relationship between etching rate and 0□ partial pressure in ion etching. 02 With the increase in partial pressure,
The etching rate of Nb and Stow decreases, and the etching rate of Pb hardly changes and is further improved by addition. Effect of addition of Ol Fi5 X 10-
' This is particularly noticeable at 02 partial pressures of Torr or higher. on the other hand,
As the 02 partial pressure increases, the etching speed ratio of the resist (AZ1350J) decreases, but if this value is below the appropriate 07 partial pressure, it will be sufficient to perform high-precision butter/transfer. Although these are the results when Nb and Pb are used as superconductor materials, similar results can be obtained with Nb compounds and Pb alloys, respectively. In addition, this method allows the use of a rectangular resist mask with good reproducibility and the ability to perform etching with strong anisotropy, making it possible to perform microfabrication with high dimensional accuracy. Furthermore, the first superconductor electrode 1
2. After successively forming the three-layer film of the tunnel barrier layer 13 and the second superconductor 14, in order to define the busy tunnel barrier section, exposure to the atmosphere and resist processing, which are problems in the conventional method shown in Fig. 3, are required. , no contamination due to sputter cleaning.
（実施例） 次に本発明の一実施例を示す。(Example) Next, one embodiment of the present invention will be described.
表面を熱酸化８１０．で被覆したシリコン（Ｓｉ）基板
上に、電子ビーム蒸着法により基板温度３００℃でＮｂ
膜２０００Ｘを被着する。引き続き、同一装置内でＯ２
を導入し、予め設定した圧力で一定時間放置してＮｂ膜
表面上に数１０大の熱酸化膜を形成する。この後、連続
して室温でｐｂ膜１５００Ｘを蒸着する。この膜上に、
ＡＺ１３５０Ｊを用いた通常を連続エツチングして第１
の超伝導体電極パターンを形成する。次に、上記３層膜
上のトンネル障壁部と彦る場所にレジストマスクをバタ
ーニングした後、Ａｒと０２との混合ガスを用いたイオ
ンエツチング法でＰｂ膜を完全に除去し、第２の超伝導
体電極パターンを形成する。エツチング条件は、０□圧
力３×１０づＴｏ ｒ ｒ 、全圧力２Ｘ１０−’ Ｔ
ａｒｔ、加速電圧５００Ｖ、電流密度０．８ ｍＡｌｃ
ｒｄである。実際にジョセフソン接合素子を形成する場
合は引き続き、基板上に２０００Ｘの８ｉ０ｉ蒸着し、
レジストマスクをアセトン中の超音波洗浄でり７トオフ
する。Thermal oxidation of the surface 810. Nb was deposited on a silicon (Si) substrate coated with Nb by electron beam evaporation at a substrate temperature of 300°C.
Deposit membrane 2000X. Continue to use O2 in the same device.
is introduced and left at a preset pressure for a certain period of time to form a thermal oxide film of several tens of sizes on the surface of the Nb film. After this, a PB film 1500X is continuously deposited at room temperature. On this membrane,
Continuous etching using AZ1350J
form a superconductor electrode pattern. Next, after patterning a resist mask on the three-layer film at a location corresponding to the tunnel barrier, the Pb film is completely removed by ion etching using a mixed gas of Ar and 02, and the second Pb film is etched. Form a superconductor electrode pattern. Etching conditions are 0□pressure 3×10 Torr, total pressure 2×10-'T
art, acceleration voltage 500V, current density 0.8 mAlc
It is rd. When actually forming a Josephson junction element, 8i0i of 2000X is deposited on the substrate,
The resist mask is cleaned off by ultrasonic cleaning in acetone.
さらに、基板表面をＡｒでスパッタクリーニングし。Furthermore, the surface of the substrate was sputter cleaned with Ar.
た後、第２の超伝導体電標パターン形成と同様な方法で
３ｏｏｏＸのＰｂ膜からがる上部配線を形成する。第２
の超伝導体電極をバターニングしてトンネル障壁部を規
定する際、ＰｂのＡＺ１３５０Ｊに対するエツチング速
度比は６と太き（，０，１１１ｙｎ以下の高精度のパタ
ーン転写が可能であう念。また、ＰｂのＮｂ、５ｉ０２
に対するエツチング速度比はそれぞれ５２．１５で、は
ぼ完全なｐｂの選択エッチ柵グを行なうことができた。After that, an upper wiring made of a 300X Pb film is formed in the same manner as in the formation of the second superconductor electrode pattern. Second
When defining the tunnel barrier section by patterning the superconductor electrode of Pb, the etching rate ratio of Pb to AZ1350J is as high as 6 (0,111yn or less). Nb, 5i02
The etch rate ratio for PB was 52.15, respectively, and almost complete selective etch of PB could be performed.
トンネル障壁層を介し木型極間のショートは全く認めら
れず、非常に良との接合特性が得られた。No short circuit between the wooden poles was observed through the tunnel barrier layer, and very good bonding characteristics were obtained.
′一本実施例では、第１の超伝導体電極としてＮｂを、
第２および第３の超伝導体電極としてＰｂｆ、用いた場
合について説明したが、それぞれＮｂ（ヒ合物、Ｐｂ合
金でも同様々結果が得られる。第３の超伝導体電極には
ＮｈあるいはＮｂ化合物を用いることもできる。また、
トンネル障壁層には第１の超伝導体電極表面の酸化層以
外に、被着により形成した絶縁体層を、トンネル障壁層
を酸化する場合罠は金属層、半導体層も適用できる。本
実施例では、トンネル障壁部を形成するためのマスクと
してＡＺ１３５０Ｊを使用したが、他の有機レジスト、
無機レジストなども用いることができる。'In this example, Nb is used as the first superconductor electrode,
Although we have explained the case where Pbf is used as the second and third superconductor electrodes, similar results can be obtained with Nb (hypothecide, Pb alloy, etc.). Compounds can also be used.Also,
In addition to the oxidized layer on the surface of the first superconductor electrode, the tunnel barrier layer may be an insulating layer formed by deposition, and when the tunnel barrier layer is oxidized, a metal layer or a semiconductor layer may be used as the trap. In this example, AZ1350J was used as a mask for forming the tunnel barrier, but other organic resists,
Inorganic resists can also be used.
（発明の効果）
以上説明したように本発明によれば、Ｎｂ系／酸化物／
ｐｂ系ジョセフソン接合で、第１の超伝導体電極、トン
ネル障壁層、第２の超伝導体電極の３層膜を連続形成す
るため、トンネル障壁部の汚染のない高品質な接合を形
成することができる。また、トンネル障壁部の規定に選
択性、異方性の優れたＡｒと０．との混合ガスをエツチ
ングガスとするイオンエツチング法を適用することから
、オーバ(Effect of the invention) As explained above, according to the present invention, Nb-based/oxide/
In a pb-based Josephson junction, a three-layer film of the first superconductor electrode, tunnel barrier layer, and second superconductor electrode is continuously formed, so a high-quality junction is formed without contamination of the tunnel barrier part. be able to. In addition, Ar and O.D., which have excellent selectivity and anisotropy, are used to define the tunnel barrier section. Since the ion etching method uses a mixed gas of
第１図（ａ）〜＜ｔＳＳ本発明のジョセフノン接合素子
の製造方法を説明する几めの主要工程における素子の断
面図、第２図はイオンエツチングにおけるエツチング速
度と０７分圧との関係を示すグラフ、第３図（ａ）〜（
ｄｌは従来のジョセフソン接合素子の製造方法を工程順
に説明するための断面図である。
図において、１１．３１は基板、１２．３２は第１の超
伝導体電極、１３はトンネル障壁層、１４は第２の超伝
導体電極、１５．３３はレジストマスク、３４は絶縁体
層である。
Ｏ２分圧 （Ｔｏｒｒ）Fig. 1(a) - <tSS A cross-sectional view of the device during the main steps to explain the method for manufacturing the Joseph non-junction device of the present invention, and Fig. 2 shows the relationship between the etching rate and the partial pressure in ion etching. Graphs shown in Figures 3(a) to (
dl is a cross-sectional view for explaining a conventional method for manufacturing a Josephson junction element in the order of steps. In the figure, 11.31 is the substrate, 12.32 is the first superconductor electrode, 13 is the tunnel barrier layer, 14 is the second superconductor electrode, 15.33 is the resist mask, and 34 is the insulator layer. be. O2 partial pressure (Torr)
Claims (1)
体電極とこの第１の超伝導体電極の一表面上のトンネル
障壁層、およびこのトンネル障壁層を介して前記第１の
超伝導体電極と対向するＰｂまたはＰｂ合金からなる第
２の超伝導体電極を有するジヨセフソン接合素子の製造
方法において、基板上に第１の超伝導体電極、この第１
の超伝導体電極上にトンネル障壁層、このトンネル障壁
層上に第２の超伝導体電極を連続形成する工程、前記第
２の超伝導体電極上のトンネル障壁部となる場所にエッ
チングマスクを形成し、ＡｒとＯ＿２との混合ガスを用
いたイオンエッチング法により前記第２の超伝導体電極
の前記エッチングマスク以外の箇所を完全にエッチング
してトンネル障壁部を規定する工程を含むことを特徴と
するジョセフソン接合素子の製造方法。a first superconductor electrode made of Nb or a Nb compound on a substrate; a tunnel barrier layer on one surface of the first superconductor electrode; In a method for manufacturing a Josephson junction element having a second superconductor electrode made of Pb or a Pb alloy facing a substrate, a first superconductor electrode on a substrate;
A step of successively forming a tunnel barrier layer on the superconductor electrode and a second superconductor electrode on this tunnel barrier layer, applying an etching mask to a location on the second superconductor electrode that will become the tunnel barrier portion. forming a tunnel barrier portion, and completely etching a portion of the second superconductor electrode other than the etching mask by an ion etching method using a mixed gas of Ar and O_2 to define a tunnel barrier portion. A method for manufacturing a Josephson junction device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188917A JPS6167975A (en) | 1984-09-11 | 1984-09-11 | Manufacture of josephson junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59188917A JPS6167975A (en) | 1984-09-11 | 1984-09-11 | Manufacture of josephson junction element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167975A true JPS6167975A (en) | 1986-04-08 |
Family
ID=16232142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59188917A Pending JPS6167975A (en) | 1984-09-11 | 1984-09-11 | Manufacture of josephson junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167975A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020580A (en) * | 2022-06-10 | 2022-09-06 | 中国科学院上海微系统与信息技术研究所 | A kind of magnetic flux storage device based on π junction and preparation method thereof |
-
1984
- 1984-09-11 JP JP59188917A patent/JPS6167975A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| APPL PHYS LETT * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020580A (en) * | 2022-06-10 | 2022-09-06 | 中国科学院上海微系统与信息技术研究所 | A kind of magnetic flux storage device based on π junction and preparation method thereof |
| CN115020580B (en) * | 2022-06-10 | 2024-11-19 | 中国科学院上海微系统与信息技术研究所 | A magnetic flux storage device based on π junction and preparation method thereof |
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